Mohamad Moner Al Chawa

Orcid: 0000-0001-8886-4708

According to our database1, Mohamad Moner Al Chawa authored at least 25 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Compact Model of Threshold Switching Devices for Efficient Circuit Simulations.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

A Behavioural Compact Model for Programmable Neuromorphic ReRAM.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Implementation of a Physically Unclonable Function using LEDs and LDRs.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2022
A Compact and Continuous Reformulation of the Strachan TaO<sub>x</sub> Memristor Model With Improved Numerical Stability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Empirical Modelling of ReRAM Measured Characteristics Using Charge and Flux.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

A Locally Active Device Model Based on a Minimal 2T1R Circuit.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022


2021
NbO<sub>2</sub>-Mott Memristor: A Circuit- Theoretic Investigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Compact Memristor Model for Neuromorphic ReRAM Devices in Flux-Charge Space.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A New Temperature-Based Model for the Reset Transition on ReRAM Memristive Devices.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

A Stochastic Switched Capacitor Memristor Emulator.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

2020
A Simple Quasi-Static Compact Model of Bipolar ReRAM Memristive Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Simple Monte Carlo Model for the Cycle-to-Cycle Reset Transition Variation of ReRAM Memristive Devices.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

A Simple Memristor Model for Neuromorphic ReRAM Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Flux-Controlled Memristor Model for Neuromorphic ReRAM Devices.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Self-learning perceptron using a digital memristor emulator.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

A Non-Quasi Static Model for Reset Voltage Variation in Memristive Devices.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Simple Piecewise Model of Reset/Set Transitions in Bipolar ReRAM Memristive Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Exploring resistive switching-based memristors in the charge-flux domain: A modeling approach.
Int. J. Circuit Theory Appl., 2018

Effective accuracy estimation and representation error reduction for stochastic logic operations.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Emulating memristors in a digital environment using stochastic logic.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Design and implementation of passive memristor emulators using a charge-flux approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Purely Digital Memristor Emulator based on a Flux-Charge Model.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors.
CoRR, 2017

An analytical delay model for ReRAM memory cells.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017


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