Mohammad Bakhshalipour

Orcid: 0000-0001-6648-1773

According to our database1, Mohammad Bakhshalipour authored at least 22 papers between 2017 and 2023.

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Bibliography

2023
Agents of Autonomy: A Systematic Study of Robotics on Modern Hardware.
Proc. ACM Meas. Anal. Comput. Syst., December, 2023

RobotPerf: An Open-Source, Vendor-Agnostic, Benchmarking Suite for Evaluating Robotics Computing System Performance.
CoRR, 2023

Runahead A*: Speculative Parallelism for A* with Slow Expansions.
Proceedings of the Thirty-Third International Conference on Automated Planning and Scheduling, 2023

2022
RTRBench: A Benchmark Suite for Real-Time Robotics.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

RACOD: algorithm/hardware co-design for mobile robot path planning.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Speculative Path Planning.
CoRR, 2021

HerQules: securing programs via hardware-enforced message queues.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers.
CoRR, 2020

Harnessing Pairwise-Correlating Data Prefetching With Runahead Metadata.
IEEE Comput. Archit. Lett., 2020

Livia: Data-Centric Computing Throughout the Memory Hierarchy.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Reducing Writebacks Through In-Cache Displacement.
ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Permanent Fault Tolerance in Hard Real-Time Systems.
IEEE Trans. Computers, 2019

Evaluation of Hardware Data Prefetchers on Server Processors.
ACM Comput. Surv., 2019

Bingo Spatial Data Prefetcher.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Fast Data Delivery for Many-Core Processors.
IEEE Trans. Computers, 2018

Die-Stacked DRAM: Memory, Cache, or MemCache?
CoRR, 2018

Making Belady-Inspired Replacement Policies More Effective Using Expected Hit Count.
CoRR, 2018

Scale-Out Processors & Energy Efficiency.
CoRR, 2018

Parallelizing Bisection Root-Finding: A Case for Accelerating Serial Algorithms in Multicore Substrates.
CoRR, 2018

Cache Replacement Policy Based on Expected Hit Count.
IEEE Comput. Archit. Lett., 2018

Domino Temporal Data Prefetcher.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
An Efficient Temporal Data Prefetcher for L1 Caches.
IEEE Comput. Archit. Lett., 2017


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