James C. Hoe

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

2021

A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem.

[BibT_eX]

[DOI]

CoRR, 2021

We need kernel interposition over the network dataplane.

[BibT_eX]

[DOI]

Proceedings of the HotOS '21: Workshop on Hot Topics in Operating Systems, 2021

HerQules: securing programs via hardware-enforced message queues.

[BibT_eX]

[DOI]

Daming D. Chen

Wen Shih Lim

Mohammad Bakhshalipour

Phillip B. Gibbons

Bryan Parno

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

High-Performance Memory Snapshotting for Real-Time, Consistent, Hypervisor-Based Monitors.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2020

Achieving 100Gbps Intrusion Prevention on a Single Server.

[BibT_eX]

[DOI]

Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation, 2020

Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

Partial Reconfiguration for Design Optimization.

[BibT_eX]

[DOI]

Nathan Serafin

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

A Service-Oriented Memory Architecture for FPGA Computing.

[BibT_eX]

[DOI]

Joseph Melber

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications.

[BibT_eX]

[DOI]

Robert Tamburo

Srinivasa G. Narasimhan

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform.

[BibT_eX]

[DOI]

Yu Wang

Eriko Nurvitadhi

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

SPIRAL: Extreme Performance Portability.

[BibT_eX]

[DOI]

Tze Meng Low

Doru-Thom Popovici

Richard Michael Veras

Daniele G. Spampinato

Proc. IEEE, 2018

Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration.

[BibT_eX]

[DOI]

CoRR, 2018

PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Using Vivado-HLS for Structural Design: a NoC Case Study.

[BibT_eX]

[DOI]

Zhipeng Zhao

CoRR, 2017

Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation.

[BibT_eX]

[DOI]

CoRR, 2017

Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only).

[BibT_eX]

[DOI]

Zhipeng Zhao

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming.

[BibT_eX]

[DOI]

Proceedings of the Deep Learning and Convolutional Neural Networks for Medical Image Computing, 2016

FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2016

HAMLeT Architecture for Parallel Data Reorganization in Memory.

[BibT_eX]

[DOI]

IEEE Micro, 2016

FPGA compute acceleration is first about energy efficiency: technical perspective.

[BibT_eX]

[DOI]

Commun. ACM, 2016

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

The CONNECT Network-on-Chip Generator.

[BibT_eX]

[DOI]

Michael K. Papamichael

Computer, 2015

Enabling portable energy efficiency with memory accelerated library.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Data reorganization in memory using 3D-stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing.

[BibT_eX]

[DOI]

Gabriel Weisz

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Nautilus: fast automated IP design space search using guided genetic algorithms.

[BibT_eX]

[DOI]

Michael K. Papamichael

Peter A. Milder

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

FPGA-Accelerated Simulation of Computer Systems

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01744-5, 2014

Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

FFTS with near-optimal memory access through block data layouts.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2014

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

GraphGen: An FPGA Framework for Vertex-Centric Graph Computation.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Understanding the design space of DRAM-optimized hardware FFT accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction.

[BibT_eX]

[DOI]

Gabriel Weisz

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Cross-platform FPGA accelerator development using CoRAM and CONNECT.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2013

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Computer Generation of Hardware for Linear Digital Signal Processing Transforms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Highly Efficient Performance Portable Tracking of Evolving Surfaces.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Improving fixed-point accuracy of FFT cores in O-OFDM systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs.

[BibT_eX]

[DOI]

Michael Papamichael

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Automatic Pipelining From Transactional Datapath Specifications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Commercial Antivirus Software Effectiveness: An Empirical Study.

[BibT_eX]

[DOI]

Orathai Sukwong

Hyong S. Kim

Computer, 2011

Integrating formal verification and high-level processor pipeline synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations.

[BibT_eX]

[DOI]

Michael Papamichael

Onur Mutlu

Proceedings of the NOCS 2011, 2011

CoRAM: an in-fabric memory architecture for FPGA-based computing.

[BibT_eX]

[DOI]

Eric S. Chung

Ken Mai

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

High Performance Stereo Vision Designed for Massively Data Parallel Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2010

High-Level Design and Validation of the BlueSPARC Multithreaded Processor.

[BibT_eX]

[DOI]

Eric S. Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

The Future of Architectural Simulation.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Fast bilateral filtering by adapting block size.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2010

Hardware implementation of the discrete fourier transform with non-power-of-two problem size.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2010

Automatic multithreaded pipeline synthesis from transactional datapath specifications.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2009

Permuting streaming data using RAMs.

[BibT_eX]

[DOI]

Peter A. Milder

J. ACM, 2009

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

Brian T. Gold

Babak Falsafi

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation.

[BibT_eX]

[DOI]

Eric S. Chung

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

2009 MEMOCODE Co-Design Contest.

[BibT_eX]

[DOI]

Forrest Brewer

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Real time stereo vision using exponential step cost aggregation on GPU.

[BibT_eX]

[DOI]

Wei Yu

Tsuhan Chen

Proceedings of the International Conference on Image Processing, 2009

Automatic generation of streaming datapaths for arbitrary fixed permutations.

[BibT_eX]

[DOI]

Peter A. Milder

Proceedings of the Design, Automation and Test in Europe, 2009

Dependable VLSI: device, design and architecture: how should they cooperate?

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

MEMOCODE 2006 guest editors' introduction.

[BibT_eX]

[DOI]

Jens Palsberg

Des. Autom. Embed. Syst., 2008

MEMOCODE 2008 Co-Design Contest.

[BibT_eX]

[DOI]

Patrick Schaumont

Krste Asanovic

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Domain-specific library generation for parallel software and hardware platforms.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Formal datapath representation and manipulation for implementing DSP transforms.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Time-Multiplexed Multiple-Constant Multiplication.

[BibT_eX]

[DOI]

Peter Tummeltshammer

Christoforos E. Kozyrakis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

RAMP: Research Accelerator for Multiple Processors.

[BibT_eX]

[DOI]

Derek Chiou

Krste Asanovic

IEEE Micro, 2007

PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

MEMOCODE 2007 Co-Design Contest.

[BibT_eX]

[DOI]

Forrest Brewer

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

FFT Compiler: from math to efficient hardware HLDVT invited short paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Generating FPGA-Accelerated DFT Libraries.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006

Statistical sampling of microarchitecture simulation.

[BibT_eX]

[DOI]

ACM Trans. Model. Comput. Simul., 2006

SimFlex: Statistical Sampling of Computer System Simulation.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Reunion: Complexity-Effective Multicore Redundancy.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Simulation sampling with live-points.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Spiral: Joint Runtime and Energy Optimization of Linear Transforms.

[BibT_eX]

[DOI]

Marek R. Telgarsky

José M. F. Moura

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Research accelerator for multiple processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

Fast and accurate resource estimation of automatically generated custom DFT IP cores.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

TRUSS: A Reliable, Scalable Server Architecture.

[BibT_eX]

[DOI]

Vasileios Liaskovitis

IEEE Micro, 2005

TurboSMARTS: accurate microarchitecture simulation sampling in minutes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2005

Automatic generation of customized discrete fourier transform IPs.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Operation-centric hardware description and synthesis.

[BibT_eX]

[DOI]

Arvind

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture.

[BibT_eX]

[DOI]

SIGMETRICS Perform. Evaluation Rev., 2004

Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth.

[BibT_eX]

[DOI]

IEEE Micro, 2004

Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Synchronous extensions to operation centric hardware description languages.

[BibT_eX]

[DOI]

Grace Nordin

Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Custom-optimized multiplierless implementations of DSP algorithms.

[BibT_eX]

[DOI]

Adam C. Zelinski

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Automatic cost minimization for multiplierless implementations of discrete signal transforms.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

In-system FPGA prototyping of an itanium microarchitecture.

[BibT_eX]

[DOI]

Roland E. Wunderlich

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Multiple constant multiplication by time-multiplexed mapping of addition chains.

[BibT_eX]

[DOI]

Peter Tummeltshammer

Proceedings of the 41th Design Automation Conference, 2004

2003

Superscalar out-of-order demystified in four instructions.

[BibT_eX]

[DOI]

Proceedings of the 2003 workshop on Computer architecture education, 2003

SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

High-level modeling and FPGA prototyping of microprocessors.

[BibT_eX]

[DOI]

Joydeep Ray

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2001

Dual use of superscalar datapath for transient-fault detection and recovery.

[BibT_eX]

[DOI]

Joydeep Ray

Babak Falsafi

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000

Operation-centric hardware description and synthesis.

[BibT_eX]

[DOI]

PhD thesis, 2000

Synthesis of Operation-Centric Hardware Descriptions.

[BibT_eX]

[DOI]

Arvind

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

A Personal Supercomputer for Climate Research.

[BibT_eX]

[DOI]

Chris Hill

Alistair Adcroft

Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Hardware Synthesis from Term Rewriting Systems.

[BibT_eX]

Arvind

Proceedings of the VLSI: Systems on a Chip, 1999

1998

MPI-StarT: Delivering Network Performance to Numerical Applications.

[BibT_eX]

[DOI]

Parry Husbands

Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

1995

START-NG: Delivering Seamless Parallel Computing.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994

Network substrate for parallel processing on a workstation cluster.

[BibT_eX]

[DOI]