Mohsen Hassanpourghadi

Orcid: 0000-0001-6410-2864

According to our database1, Mohsen Hassanpourghadi authored at least 17 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A Novel Multi-Objective Optimization Framework for Analog Circuit Customization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022
A 10-GS/s 8-bit 2850-μm<sup>2</sup> Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC.
IEEE J. Solid State Circuits, 2022

A 10GS/s 8b 25fJ/c-s 2850um<sup>2</sup> Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation.
IEEE J. Solid State Circuits, 2018

2017
A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
A low-power low-offset dynamic comparator for analog to digital converters.
Microelectron. J., 2014

2013
Fast Static Characterization of Residual-Based ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Step response analysis of third order OpAmps With slew-rate.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013


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