Mustafa Altun
Orcid: 0000-0002-3103-1809
According to our database1,
Mustafa Altun
authored at least 59 papers
between 2007 and 2023.
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Bibliography
2023
Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks.
Circuits Syst. Signal Process., 2023
2022
Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches.
IEEE Trans. Emerg. Top. Comput., 2022
TALIPOT: Energy-Efficient DNN Booster Employing Hybrid Bit Parallel-Serial Processing in MSB-First Fashion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 18th International Conference on Synthesis, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
CoRR, 2021
IEEE Access, 2021
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
2020
IEEE Trans. Computers, 2020
Systematic synthesis of approximate adders and multipliers with accurate error calculations.
Integr., 2020
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Novel Method for the Realization of Complex Logic Functions using Switching Lattices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays.
IEEE Trans. Emerg. Top. Comput., 2019
Microelectron. J., 2019
Integr., 2019
Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates.
IEEE Access, 2019
Circuit Aware Approximate System Design With Case Studies in Image Processing and Neural Networks.
IEEE Access, 2019
Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach.
IEEE Access, 2019
Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays.
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Micro, 2018
ACM Comput. Surv., 2018
From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks.
CoRR, 2018
Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits.
IEEE Access, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
J. Multiple Valued Log. Soft Comput., 2017
Microprocess. Microsystems, 2017
Distinct degradation processes in ZnO varistors: reliability analysis and modeling with accelerated AC tests.
Turkish J. Electr. Eng. Comput. Sci., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Sobel filter operation in image processing via stochastic arithmetic-logic unit design.
Proceedings of the 25th Signal Processing and Communications Applications Conference, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Reliab. Eng. Syst. Saf., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2012
2011
Robust Computation through Percolation: Synthesizing Logic with Percolation in Nanoscale Lattices.
Int. J. Nanotechnol. Mol. Comput., 2011
2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Proceedings of the 46th Design Automation Conference, 2009
2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007