Dan Alexandrescu

According to our database1, Dan Alexandrescu authored at least 37 papers between 2002 and 2019.

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Bibliography

2019
Challenges of Reliability Assessment and Enhancement in Autonomous Systems.
CoRR, 2019

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019

2018
Integrated Synthesis Methodology for Crossbar Arrays.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Techniques for heavy ion microbeam analysis of FPGA SER sensitivty.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

A call for cross-layer and cross-domain reliability analysis and management.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

The future of fault tolerant computing.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Managing SER costs of complex systems through Linear Programming.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.
Proceedings of the 19th IEEE European Test Symposium, 2014

INFORMER: An integrated framework for early-stage memory robustness analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A Practical Approach to Single Event Transient Analysis for Highly Complex Design.
J. Electronic Testing, 2013

Pulse-length determination techniques in the rectangular single event transient fault model.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Hierarchical RTL-based combinatorial SER estimation.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

State-aware single event analysis for sequential logic.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
A real-case application of a synergetic design-flow-oriented SER analysis.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

RIIF - Reliability information interchange format.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Towards optimized functional evaluation of SEE-induced failures in complex designs.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A comprehensive soft error analysis methodology for SoCs/ASICs memory instances.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Practical Approach to Single Event Transients Analysis for Highly Complex Designs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Panel: Reliability of data centers: Hardware vs. software.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Highs and lows of radiation testing.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Systematical Method of Quantifying SEU FIT.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2004
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.
J. Electronic Testing, 2004

2002
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002


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