Luca Frontini

Orcid: 0000-0002-1137-8629

According to our database1, Luca Frontini authored at least 27 papers between 2012 and 2023.

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Bibliography

2023
Modelling and Verification of MOS Transistors at Cryogenic Temperature.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023


2022
The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2020
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices.
J. Electron. Test., 2020

2019
Design and synthesis of high density integrated circuits.
PhD thesis, 2019

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.
Proceedings of the IEEE Latin American Test Symposium, 2019

Testability of Switching Lattices in the Cellular Fault Model.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Composition of switching lattices for regular and for decomposed functions.
Microprocess. Microsystems, 2018

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.
Microprocess. Microsystems, 2018

Testability of Switching Lattices in the Stuck at Fault Model.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Integrated Synthesis Methodology for Crossbar Arrays.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A very compact population count circuit for associative memories.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

A Digitally-Controlled Ring Oscillator in 28 nm CMOS technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Characterization of New Content Addressable Memory Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


2017
Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocess. Microsystems, 2017

Power Distribution Network optimization for Associative Memories.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Population count circuits for Associative Memories: A comparison study.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

A low-power and high-density Associative Memory in 28 nm CMOS technology.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Synthesis on switching lattices of Dimension-reducible Boolean functions.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


2014
Radiation-tolerant standard cell synthesis using double-rail redundant approach.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012
A new XOR-based Content Addressable Memory architecture.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


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