Nalesh S

According to our database, Nalesh S authored at least 25 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A physically unclonable function architecture with multiple responses on FPGA.

M. A. Muneeb, Nalesh S, S. Kala

Int. J. Embed. Syst., 2023

MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles.

Noble G, Nalesh S, S. Kala

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Approximate CNN on FPGA Using Toom-Cook Multiplier.

Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2022

Adiabatic Physical Unclonable Function Using Cross-Coupled Pair.

Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

Hardware Acceleration of SpMV Multiplier for Deep Learning.

Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA.

Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA.

Mahesh M, Nalesh S, S. Kala

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Fast Booth Multipliers Using Approximate 4: 2 Compressors.

S. Sreeparvathy, Rachana George, Rose Mary Kuruvithadam, Nalesh S

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2019

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture.

S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan

IEEE Trans. Very Large Scale Integr. Syst., 2019

Radix-4³ based two-dimensional FFT architecture with efficient data reordering scheme.

S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan

IET Comput. Digit. Tech., 2019

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.

S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Efficient Hardware Acceleration of Convolutional Neural Networks.

S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

A Hardware Architecture for Radial Basis Function Neural Network Classifier.

Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy

IEEE Trans. Parallel Distributed Syst., 2018

Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.

S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Two dimensional FFT architecture based on radix-4³ algorithm with efficient output reordering.

S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

Energy aware synthesis of application kernels through composition of data-paths on a CGRA.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Integr., 2017

2016

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.

Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.

S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

J. Low Power Electron., 2015

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.

Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan

Proceedings of the 28th International Conference on VLSI Design, 2015

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Compiling HPC Kernels for the REDEFINE CGRA.

Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.

Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan

J. Syst. Archit., 2014

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.

Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.

S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.

S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013