Nicholas P. Carter

According to our database1, Nicholas P. Carter authored at least 30 papers between 1992 and 2013.

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Bibliography

2013
Runnemede: An architecture for Ubiquitous High-Performance Computing.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2011
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Vision for cross-layer optimization to address the dual challenges of energy and reliability.
Proceedings of the Design, Automation and Test in Europe, 2010

Design techniques for cross-layer resilience.
Proceedings of the Design, Automation and Test in Europe, 2010

2007
Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices.
IEEE Trans. Computers, 2007

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor.
Microprocess. Microsystems, 2007

A magnetoelectronic register file cell for a self-checkpointing microprocessor.
Int. J. Circuit Theory Appl., 2007

2006
Modeling wire delay, area, power, and performance in a simulation infrastructure.
IBM J. Res. Dev., 2006

2005
Gated hybrid Hall effect device on silicon.
Microelectron. J., 2005

Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hall-effect circuits and architectures for non-volatile system design.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Reconfigurable magnetoelectronic circuits for threshold logic.
Int. J. Circuit Theory Appl., 2004

Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction.
IEEE Comput. Archit. Lett., 2004

A reconfigurable unit for a clustered programmable-reconfigurable processor.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A magnetoelectronic macrocell employing reconfigurable threshold logic.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Microprocessor Interfacing Laboratory.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Mapping computation kernels to clustered programmable-reconfigurable processors.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Reconfigurable Circuits Using Hybrid Hall Effect Devices.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Clustered programmable-reconfigurable processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

The Design of the Amalgam Reconfigurable Cluster.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2000
Processor Mechanisms for Software Shared Memory.
Proceedings of the High Performance Computing, Third International Symposium, 2000

1999
Processor mechanisms for software shared memory.
PhD thesis, 1999

1998
An Efficient, Protected Message Interface.
Computer, 1998

Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
The M-machine multicomputer.
Int. J. Parallel Program., 1997

1994
Conversion of the Haydn symphonies into electronic form using automatic score recognition: a pilot study.
Proceedings of the Document Recognition, San Jose, CA, USA, February 6, 1994, 1994

Hardware Support for Fast Capability-based Addressing.
Proceedings of the ASPLOS-VI Proceedings, 1994

1992
Segmentation and preliminary recognition of madrigals notated in white mensural notation.
Mach. Vis. Appl., 1992


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