O. Sam Nakagawa

According to our database1, O. Sam Nakagawa authored at least 10 papers between 1996 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2002
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Instruction Prediction for Step Power Reduction.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Ramp Up/Down Functional Unit to Reduce Step Power.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Full Chip Thermal Simulation.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Quick On-Chip Self- and Mutual-Inductance Screen.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Clocktree RLC Extraction with Efficient Inductance Modeling.
Proceedings of the 2000 Design, 2000

1999
An efficient inductance modeling for on-chip interconnects.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


  Loading...