Zhiping Yu
According to our database1,
Zhiping Yu
authored at least 76 papers
between 1987 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to modeling and simulation of advanced semiconductor devices".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis.
CoRR, 2023
2018
Wideband Inductorless Low-Power LNAs with G<sub>m</sub> Enhancement and Noise-Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Study on scalability of hybrid junctionless FinFET and multi-stacked nanowire FET by TCAD simulation.
IEICE Electron. Express, 2018
Sci. China Inf. Sci., 2018
An Accurate dB-Linear Programmable-Gain Amplifier with Temperature-Robust Characteristic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 60-GHz 360° 5-Bit Phase Shifter With Constant IL Compensation Followed by a Normal Amplifier With ±1 dB Gain Variation and 0.6-dBm OP<sub>-1dB</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Sci. China Inf. Sci., 2017
2016
J. Commun. Inf. Networks, 2016
2015
Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Fast Convolution Method and Its Application in Mask Optimization for Intensity Calculation Using Basis Expansion.
IEEE Trans. Image Process., 2014
A 3.45-4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
An inductorless wideband low noise amplifier with current reuse and linearity enhancement.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Image Process., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A low-power ESD-protected 24GHz receiver front-end with π-type input matching network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
High performance source optimization using a gradient-based method in optical lithography.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A comprehensive model for gate delay under process variation and different driving and loading conditions.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis.
Proceedings of the 47th Design Automation Conference, 2010
A novel wideband 1-π model with accurate substrate modeling for on-chip spiral inductors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
Design and Implementation of Ultralow Current-Mode Amplifier for Biosensor Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Integr., 2009
An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation.
Proceedings of the Design, Automation and Test in Europe, 2008
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification.
Proceedings of the 45th Design Automation Conference, 2008
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Improvement Techniques for the EM-Based Neural Network Approach in RF Components Modeling.
Proceedings of the Advances in Neural Networks, 2007
Design and Verification of Ultra Low Current Mode Amplifier Aiming at Biosensor Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage.
Proceedings of the 44th Design Automation Conference, 2007
2006
Fast algorithm for bandstructure calculation in silicon nanowires using supercell approach.
Int. J. Comput. Sci. Eng., 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Computation of Si Nanowire Bandstructures on Parallel Machines Through Domain Decomposition.
Proceedings of the Computational Science, 2006
Parasitics extraction involving 3-D conductors based on multi-layered Green's function.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A Novel Solid Neuron-Network Chip Based on Both Biological and Artificial Neural Network Theories.
Proceedings of the Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30, 2005
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
2001
Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1998
Second Order Newton Iteration Method and Its Application to MOS Compact Modeling and Circuit Simulation.
VLSI Design, 1998
Observation of Anomalous Negative Differential Resistance in Diode Breakdown Simulation Using Carrier Temperature Dependent Impact Ionization.
VLSI Design, 1998
1995
Formulation of Macroscopic Transport Models for Numerical Simulation of Semiconductor Devices.
VLSI Design, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
1993
Modeling of the charge balance condition on floating gates and simulation of EEPROMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Technology CAD - computer simulation of IC processes and devices.
The Kluwer international series in engineering and computer science 243, Kluwer, ISBN: 978-0-7923-9379-5, 1993
1991
Proceedings of the 28th Design Automation Conference, 1991
1990
A nonequilibrium one-dimensional quantum-mechanical simulation for AlGaAs/GaAs HEMT structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1987
An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987