Jihong Ren

According to our database1, Jihong Ren authored at least 18 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.
IEEE J. Solid State Circuits, 2011

2010
Equalizer design and performance trade-offs in ADC-based serial links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Simulation and Analysis of Random Decision Errors in Clocked Comparators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Stochastic steady-state and AC analyses of mixed-signal systems.
Proceedings of the 46th Design Automation Conference, 2009

2008
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008

Characterization of random decision errors in clocked comparators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
An efficient linear programming solver for optimal filter synthesis.
Numer. Linear Algebra Appl., 2007

A Jitter Attenuating Timing Chain.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
Surfing Interconnect.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
A unified optimization framework for equalization filter synthesis.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Crosstalk Cancellation for Realistic PCB Buses.
Proceedings of the Integrated Circuit and System Design, 2004

A Signal Integrity Test Bed for PCB Buses.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Equalizing Filter Design for Crosstalk Cancellation.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Synthesizing optimal filters for crosstalk-cancellation for high-speed buses.
Proceedings of the 40th Design Automation Conference, 2003


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