Sandro Rigo

Affiliations:
  • University of Campinas, Sao Paulo, Brazil


According to our database1, Sandro Rigo authored at least 44 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
LLMs and Translation: different approaches to localization between Brazilian Portuguese and European Portuguese.
Proceedings of the 16th International Conference on Computational Processing of Portuguese, 2024

2023
Relating Edge Computing and Microservices by means of Architecture Approaches and Features, Orchestration, Choreography, and Offloading: A Systematic Literature Review.
CoRR, 2023

2022
Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

The OpenMP Cluster Programming Model.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

2021
Employing Simulation to Facilitate the Design of Dynamic Binary Translators.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2020
Binary Segmentation of Seismic Facies Using Encoder-Decoder Neural Networks.
CoRR, 2020

Employing Simulation to Facilitate the Design of Dynamic Code Generators.
CoRR, 2020

Simulating Smart Campus Applications in Edge and Fog Computing.
Proceedings of the IEEE International Conference on Smart Computing, 2020

2019
Similarity Driven Approximation for Text Analytics.
CoRR, 2019

Approximation with Error Bounds in Spark.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

2018
Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-Based Applications.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Uncertainty Propagation in Data Processing Systems.
Proceedings of the ACM Symposium on Cloud Computing, 2018

2017
HybridVerifier: A Cross-Platform Verification Framework for Instruction Set Simulators.
IEEE Embed. Syst. Lett., 2017

2014
Adaptive global power optimization for Web servers.
J. Supercomput., 2014

Empirical and analytical approaches for web server power modeling.
Clust. Comput., 2014

Leveraging Optimization Methods for Dynamically Assisted Control-Flow Integrity Mechanisms.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Assessing computer performance with stocs.
Proceedings of the ACM/SPEC International Conference on Performance Engineering, 2013

Modeling virtual machines misprediction overhead.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

2012
Data center power and performance optimization through global selection of P-states and utilization rates.
Sustain. Comput. Informatics Syst., 2012

Computational reflection and its application to platform verification.
Des. Autom. Embed. Syst., 2012

Compressing Variable-Length Instruction Traces.
Proceedings of the 13th Symposium on Computer Systems, 2012

Optimizing Simulation in Multiprocessor Platforms Using Dynamic-Compiled Simulation.
Proceedings of the 13th Symposium on Computer Systems, 2012

2011
Assessing the influence of data access patterns and contention management policies on the performance of software transactional memory systems.
Int. J. High Perform. Syst. Archit., 2011

Using multiple abstraction levels to speedup an MPSoC virtual platform simulator.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Empirical Web server power modeling and characterization.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

2010
STM versus lock-based systems: an energy consumption perspective.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
An early real-time checker for retargetable compile-time analysis.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A novel verification technique to uncover out-of-order DUV behaviors.
Proceedings of the 46th Design Automation Conference, 2009

2008
An open-source binary utility generator.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Automatic Retargeting of Binary Utilities for Embedded Code Generation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A computational reflection mechanism to support platform debugging in SystemC.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005
The ArchC Architecture Description Language and Tools.
Int. J. Parallel Program., 2005

Platform designer: An approach for modeling multiprocessor platforms based on SystemC.
Des. Autom. Embed. Syst., 2005

Extending the ArchC Language for Automatic Generation of Assemblers.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

2004
ArchC: uma linguagem de descrição de arquiteturas.
PhD thesis, 2004

Teaching computer architecture using an architecture description language.
Proceedings of the 2004 workshop on Computer architecture education, 2004

ArchC: A SystemC-Based Architecture Description Language.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Optimizations for Compiled Simulation Using Instruction Type Information.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.
Proceedings of the 2004 Design, 2004

2003
Exploring Memory Hierarchy with ArchC.
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

2001
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Optimal Live Range Merge for Address Register Allocation in Embedded Programs.
Proceedings of the Compiler Construction, 10th International Conference, 2001


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