Pedro Benedicte

According to our database, Pedro Benedicte authored at least 20 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Smart hardware designs for probabilistically-analyzable processor architectures.

Pedro Benedicte Illescas

PhD thesis, 2022

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform.

Pablo Andreu, Carles Hernández, Tomás Picornell, Pedro López, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella

CoRR, 2022

SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks.

Fabio Mazzocchetti, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella

CoRR, 2022

SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications.

Ramon Canal, Francisco Bas, Sergi Alcaide, Guillem Cabo, Pedro Benedicte, Francisco Fuentes, Feng Chang, Ilham Lasfar, Jaume Abella

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems.

Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Francisco Fuentes, Feng Chang, Ilham Lasfar, Ramon Canal, Jaume Abella

Proceedings of the Forum on Specification & Design Languages, 2022

De-RISC: A Complete RISC-V Based Space-Grade Platform.

Nils-Johan Wessman, Fabio Malatesta, Stefano Ribes, Jan Andersson, Antonio García-Vilanova, Miguel Masmano, Vicente Nicolau, Paco Gomez, Jimmy Le Rhun, Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Jaume Abella

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SafeSU-2: a Safe Statistics Unit for Space MPSoCs.

Guillem Cabo, Sergi Alcaide, Carles Hernández, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores.

Francisco Bas, Pedro Benedicte, Sergi Alcaide, Guillem Cabo, Fabio Mazzocchetti, Jaume Abella

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs.

Hamid Tabani, Fabio Mazzocchetti, Pedro Benedicte, Jaume Abella, Francisco J. Cazorla

J. Parallel Distributed Comput., 2021

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation.

Oriol Sala, Sergi Alcaide, Guillem Cabo, Francisco Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Guillermo Gil, Fabio Mazzocchetti, Jaume Abella

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

2020

Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP).

Jeremy Giesen, Pedro Benedicte, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

2019

Locality-aware cache random replacement policies.

Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla

J. Syst. Archit., 2019

Performance Analysis and Optimization of Automotive GPUs.

Fabio Mazzocchetti, Pedro Benedicte, Hamid Tabani, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla

Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache.

Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Towards limiting the impact of timing anomalies in complex real-time processors.

Pedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

RPR: a random replacement policy with limited pathological replacements.

Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems.

Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 30th Euromicro Conference on Real-Time Systems, 2018

Design and integration of hierarchical-placement multi-level caches for real-time systems.

Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016

Modelling the confidence of timing analysis for time randomised caches.

Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla

Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

A confidence assessment of WCET estimates for software time randomized caches.

Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla

Proceedings of the 14th IEEE International Conference on Industrial Informatics, 2016