Philippe Hoogvorst

According to our database1, Philippe Hoogvorst authored at least 29 papers between 1991 and 2015.

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Bibliography

2015
Improving the Big Mac Attack on Elliptic Curve Cryptography.
IACR Cryptol. ePrint Arch., 2015

2013
A synthesis of side-channel attacks on elliptic curve cryptography in smart-cards.
J. Cryptogr. Eng., 2013

Dynamic Countermeasure Against the Zero Power Analysis.
IACR Cryptol. ePrint Arch., 2013

2012
Tampering with Java Card Exceptions - The Exception Proves the Rule.
Proceedings of the SECRYPT 2012, 2012

Application-Replay Attack on Java Cards: When the Garbage Collector Gets Confused.
Proceedings of the Engineering Secure Software and Systems - 4th International Symposium, 2012

Same Values Power Analysis Using Special Points on Elliptic Curves.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

Low-Cost Countermeasure against RPA.
Proceedings of the Smart Card Research and Advanced Applications, 2012

2011
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
CoRR, 2011

Java Card Operand Stack: Fault Attacks, Combined Attacks and Countermeasures.
Proceedings of the Smart Card Research and Advanced Applications, 2011

2010
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.
IEEE Trans. Computers, 2010

2009
High speed true random number generator based on open loop structures in FPGAs.
Microelectron. J., 2009

2008
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.
IEEE Trans. Computers, 2008

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
CoRR, 2008

Place-and-Route Impact on the Security of DPL Designs in FPGAs.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.
Proceedings of the FPL 2008, 2008

Efficient tiling patterns for reconfigurable gate arrays.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

An 8x8 run-time reconfigurable FPGA embedded in a SoC.
Proceedings of the 45th Design Automation Conference, 2008

Physical Design of FPGA Interconnect to Prevent Information Leakage.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
A fast pipelined multi-mode DES architecture operating in IP representation.
Integr., 2007

Template Attacks with a Power Model.
IACR Cryptol. ePrint Arch., 2007

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.
IEEE Des. Test Comput., 2007

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Novel Asynchronous e-FPGA Architecture for Security Applications.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005
The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations.
Proceedings of the Security and Privacy in the Age of Ubiquitous Computing, IFIP TC11 20th International Conference on Information Security (SEC 2005), May 30, 2005

The "Backend Duplication" Method.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
CMOS Structures Suitable for Secured Hardware.
Proceedings of the 2004 Design, 2004

Differential Power Analysis Model and Some Results.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

1991
POMP or How to Design a Massively Parallel Machine with Small Developments.
Proceedings of the PARLE '91: Parallel Architectures and Languages Europe, 1991


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