Tarik Graba

According to our database1, Tarik Graba authored at least 33 papers between 2006 and 2023.

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Bibliography

2023
Jitter Compensation Mechanism for Dynamic Deterministic Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021

RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.
IEEE Trans. Computers, 2020

RISC-V Extension for Lightweight Cryptography.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers.
Proceedings of the Information Security Theory and Practice, 2018

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Cryptographically Secure Shield for Security IPs Protection.
IEEE Trans. Computers, 2017

Multi-level formal verification - A new approach against fault injection attack.
J. Cryptogr. Eng., 2017

2016
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology.
CoRR, 2016

2015
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur., 2015

Hardware implementation of all digital calibration for undersampling TIADCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System.
IACR Cryptol. ePrint Arch., 2014

Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.
Proceedings of the HASP 2014, 2014

Cryptographically secure shields.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

A look into SIMON from a side-channel perspective.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

Studying Leakages on an Embedded Biometric System Using Side Channel Analysis.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

2013
Stochastic Model of a Metastability-Based True Random Number Generator.
Proceedings of the Trust and Trustworthy Computing - 6th International Conference, 2013

Design methodology of an ASIC TRNG based on an open-loop delay chain.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

FPGA Design of an Open-Loop True Random Number Generator.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Efficient Dual-Rail Implementations in FPGA Using Block RAMs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2009
A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule.
EURASIP J. Embed. Syst., 2009

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

WDDL is Protected against Setup Time Violation Attacks.
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009

2008
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

Place-and-Route Impact on the Security of DPL Designs in FPGAs.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

2006
An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor.
Proceedings of the 13th IEEE International Conference on Electronics, 2006


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