Laurent Sauvage

Orcid: 0000-0002-6940-6856

According to our database¹, Laurent Sauvage authored at least 37 papers between 2008 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of three.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2023

Quasi-linear Masking to Protect Kyber against both SCA and FIA.

[BibT_eX]

[DOI]

Pierre-Augustin Berthet

Cédric Tavernier

Jean-Luc Danger

Laurent Sauvage

IACR Cryptol. ePrint Arch., 2023

Investigating Efficient Deep Learning Architectures For Side-Channel Attacks on AES.

[BibT_eX]

[DOI]

Yohaï-Eliel Berreby

Laurent Sauvage

CoRR, 2023

High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA.

[BibT_eX]

[DOI]

Arnaud Varillon

Laurent Sauvage

Jean-Luc Danger

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023

A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023

Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021

Formal Evaluation and Construction of Glitch-resistant Masked Functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

2020

Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer.

[BibT_eX]

[DOI]

Oualid Trabelsi

Laurent Sauvage

Jean-Luc Danger

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019

Cache-Timing Attacks Still Threaten IoT Devices.

[BibT_eX]

[DOI]

Proceedings of the Codes, Cryptology and Information Security, 2019

2018

Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

2017

Multi-level formal verification - A new approach against fault injection attack.

[BibT_eX]

[DOI]

Laurent Sauvage

Tarik Graba

Thibault Porteboeuf

J. Cryptogr. Eng., 2017

How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

2016

Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Differential Fault Analysis on Midori.

[BibT_eX]

[DOI]

Wei Cheng

Yongbin Zhou

Laurent Sauvage

Proceedings of the Information and Communications Security - 18th International Conference, 2016

2015

High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

2014

Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.

[BibT_eX]

[DOI]

Nicolas Veyrat-Charvillon

Matthieu Walle

Antoine Wurcker

J. Cryptogr. Eng., 2014

Hardware Trojan Horses in Cryptographic IP Cores.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

A Pre-processing Composition for Secret Key Recovery on Android Smartphone.

[BibT_eX]

[DOI]

Proceedings of the Information Security Theory and Practice. Securing the Internet of Things, 2014

2012

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

A Small and High-Performance Coprocessor for Fingerprint Match-on-Card.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Performance evaluation of protocols resilient to physical attacks.

[BibT_eX]

[DOI]

Proceedings of the HOST 2011, 2011

2010

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2010

Cross-Correlation Cartography.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Defeating Any Secret Cryptography with SCARE Attacks.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2010

Fault Injection Resilience.

[BibT_eX]

[DOI]

Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010

Far Correlation-based EMA with a precharacterized leakage model.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the Topics in Cryptology, 2010

2009

Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.

[BibT_eX]

[DOI]

Laurent Sauvage

Sylvain Guilley

Yves Mathieu

ACM Trans. Reconfigurable Technol. Syst., 2009

DPL on Stratix II FPGA: What to Expect?.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

Place-and-Route Impact on the Security of DPL Designs in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Silicon-level Solutions to Counteract Passive and Active Attacks.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

Laurent Sauvage

Timeline

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On csauthors.net:

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