Pieter De Wit

According to our database, Pieter De Wit authored at least 13 papers between 2008 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS.

Pieter De Wit, Georges G. E. Gielen

IEEE J. Solid State Circuits, 2012

Offset measurement method for accurate characterization of BTI-induced degradation in opamps.

Swaraj Mahato, Pieter De Wit, Elie Maricau, Georges G. E. Gielen

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Designing reliable analog circuits in an unreliable world.

Georges G. E. Gielen, Elie Maricau, Pieter De Wit

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS.

Simon Vanden Bussche, Pieter De Wit, Elie Maricau, Georges G. E. Gielen

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A failure-resilient xDSL line driver with on-chip degradation monitor.

Pieter De Wit, Georges G. E. Gielen

Proceedings of the 37th European Solid-State Circuits Conference, 2011

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation.

Georges G. E. Gielen, Elie Maricau, Pieter De Wit

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Efficient simulation model for DAC dynamic properties.

Pieter De Wit, Georges G. E. Gielen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design automation towards reliable analog integrated circuits.

Georges G. E. Gielen, Elie Maricau, Pieter De Wit

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001].

Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel Steyaert

IEEE J. Solid State Circuits, 2009

A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM.

Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel S. J. Steyaert

IEEE J. Solid State Circuits, 2009

2008

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications.

Elie Maricau, Pieter De Wit, Georges G. E. Gielen

Microelectron. Reliab., 2008

A fully-integrated Wienbridge topology for ultra-low-power 86ppm/°C 65nm CMOS 6MHz clock reference with amplitude regulation.

Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel Steyaert

Proceedings of the ESSCIRC 2008, 2008

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.

Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría

Proceedings of the Design, Automation and Test in Europe, 2008