Javier Martín-Martínez
Orcid: 0000-0001-5938-5898
According to our database1,
Javier Martín-Martínez
authored at least 51 papers
between 2007 and 2023.
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Bibliography
2023
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.
Proceedings of the 19th International Conference on Synthesis, 2023
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.
IEEE Trans. Instrum. Meas., 2022
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Power-Efficient Noise-Induced Reduction of ReRAM Cell's Temporal Variability Effects.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas., 2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr., 2020
Experimental Monitoring of Aging in CMOS RF Linear Power Amplifiers: Correlation Between Device and Circuit Degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
IEEE J. Solid State Circuits, 2019
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
Proceedings of the 15th International Conference on Synthesis, 2018
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Investigation of Conductivity Changes in Memristors under Massive Pulsed Characterization.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Proceedings of the 14th International Conference on Synthesis, 2017
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Integr., 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Threshold voltage and on-current Variability related to interface traps spatial distribution.
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture.
Microelectron. Reliab., 2014
2013
Influence of the interface trap location on the performance and variability of ultra-scaled MOSFETs.
Microelectron. Reliab., 2013
Resistive switching like-behavior in MOSFETs with ultra-thin HfSiON dielectric gate stack: pMOS and nMOS comparison and reliability implications.
Microelectron. Reliab., 2013
2012
Characterization and SPICE modeling of the CHC related time-dependent variability in strained and unstrained pMOSFETs.
Microelectron. Reliab., 2012
Unified characterization of RTN and BTI for circuit performance and variability simulation.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2010
SPICE modelling of hot-carrier degradation in Si<sub>1-</sub><sub>x</sub>Ge<sub>x</sub> S/D and HfSiON based pMOS transistors.
Microelectron. Reliab., 2010
2009
Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks.
Microelectron. Reliab., 2009
Reversible dielectric breakdown in ultrathin Hf based high-k stacks under current-limited stresses.
Microelectron. Reliab., 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror.
Microelectron. Reliab., 2007
Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs.
Microelectron. Reliab., 2007