Stephen Neuendorffer

Orcid: 0000-0003-2956-8428

Affiliations:
  • Xilinx, USA


According to our database1, Stephen Neuendorffer authored at least 29 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
IRFuzzer: Specialized Fuzzing for LLVM Backend Code Generation.
CoRR, 2024

An End-to-End Programming Model for AI Engine Architectures.
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024

2023
Special Issue: "AI Acceleration on FPGAs".
ACM Trans. Embed. Comput. Syst., November, 2023

SPADES: A Productive Design Flow for Versal Programmable Logic.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
Introduction to Special Issue on FPGAs in Data Centers, Part II.
ACM Trans. Reconfigurable Technol. Syst., 2022

Introduction to Special Issue on FPGAs in Data Centers.
ACM Trans. Reconfigurable Technol. Syst., 2022

FPGA HLS Today: Successes, Challenges, and Opportunities.
ACM Trans. Reconfigurable Technol. Syst., 2022

ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Compiler-Driven Simulation of Reconfigurable Hardware Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
ScaleHLS: Scalable High-Level Synthesis through MLIR.
CoRR, 2021

2020
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2018
Parallel Programming for FPGAs.
CoRR, 2018

2013
Building zynq® accelerators with Vivado® high level synthesis.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
Classes and inheritance in actor-oriented design.
ACM Trans. Embed. Comput. Syst., 2009

Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Streaming Systems in FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, 2008

2007
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Combining module selection and resource sharing for efficient FPGA pipeline synthesis.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2004
Modeling Real-World Control Systems: Beyond Hybrid Systems.
Proceedings of the 36th conference on Winter simulation, 2004

Hierarchical reconfiguration of dataflow models.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Classes and subclasses in actor-oriented design.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

2003
Taming heterogeneity - the Ptolemy approach.
Proc. IEEE, 2003

Actor-Oriented Design of Embedded Hardware and Software Systems.
J. Circuits Syst. Comput., 2003

2002
Reprogrammable Platforms for High-Speed Data Acquisition.
Des. Autom. Embed. Syst., 2002


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