Pratap Tumkur Renukaswamy

According to our database, Pratap Tumkur Renukaswamy authored at least 6 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC.

Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.

Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.

Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.

Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx

IEEE J. Solid State Circuits, 2020

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.

Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.

Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx

IEEE J. Solid State Circuits, 2019