Barend van Liempd
Orcid: 0000-0001-6877-8116
According to our database1,
Barend van Liempd
authored at least 33 papers
between 2010 and 2022.
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Bibliography
2022
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
2-D Localization, Angular Separation and Vital Signs Monitoring Using a SISO FMCW Radar for Smart Long-Term Health Monitoring Environments.
IEEE Internet Things J., 2021
Convergent Communication, Sensing and Localization in 6G Systems: An Overview of Technologies, Opportunities and Challenges.
IEEE Access, 2021
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 2019 IEEE Conference on Computer Communications, 2019
2018
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA.
IEEE J. Solid State Circuits, 2018
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An In-Band Full-Duplex Transceiver for Simultaneous Communication and Environmental Sensing.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
Proceedings of the 2017 IEEE International Symposium on Dynamic Spectrum Access Networks, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power.
Proceedings of the ESSCIRC Conference 2015, 2015
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the IEEE International Symposium on Dynamic Spectrum Access Networks, 2015
Proceedings of the 20th IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2015
2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014
IEEE J. Sel. Areas Commun., 2014
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014
A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation.
Proceedings of the 1st International Conference on 5G for Ubiquitous Connectivity, 2014
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010