Pushan Tang

According to our database1, Pushan Tang authored at least 12 papers between 1989 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2010
Intel LVS logic as a combinational logic paradigm in CNT technology.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

2007
Solving SAT problem by heuristic polarity decision-making algorithm.
Sci. China Ser. F Inf. Sci., 2007

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Integrating advanced reasoning into a SAT solver.
Sci. China Ser. F Inf. Sci., 2005

Sequential equivalence checking using cuts.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2001
Relaxation Algorithm of Piecing-Error for Sub-Images.
J. Comput. Sci. Technol., 2001

2000
Parasitic and mismatch modeling for optimal stack generation [in CMOS].
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A constraint-based placement refinement method for CMOS analog cell layout.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Analytical Delay Model for SRAM-Based FPGA Interconnections.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm.
Proceedings of the ASP-DAC '98, 1998

1989
Global refinement for building block layout.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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