Bao Liu

According to our database1, Bao Liu authored at least 80 papers between 2001 and 2020.

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Bibliography

2020
A many-objective evolutionary algorithm based on decomposition with dynamic resource allocation for irregular optimization.
Frontiers Inf. Technol. Electron. Eng., 2020

Design of ETL Tool for Structured Data Based on Data Warehouse.
Proceedings of the CSAE 2020: The 4th International Conference on Computer Science and Application Engineering, 2020

2019
模糊自适应排序变异多目标差分进化算法 (Multi-objective Differential Evolution Algorithm with Fuzzy Adaptive Ranking-based Mutation).
计算机科学, 2019

The Optimization Algorithm of the Forced Current Cathodic Protection Base on Simulated Annealing.
Algorithms, 2019

Real-Time Guidewire Segmentation and Tracking in Endovascular Aneurysm Repair.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Design of Intelligent Home Lighting Control System Based on Speech Recognition.
Proceedings of the Green Energy and Networking - 6th EAI International Conference, 2019

Design and Implementation of Intelligent Car for Light Environment Detection Based on Data Analysis.
Proceedings of the Green Energy and Networking - 6th EAI International Conference, 2019

Research on Illumination Estimation Based on Data Fitting.
Proceedings of the Green Energy and Networking - 6th EAI International Conference, 2019

2018
Short Paper: Damage Mechanism and Risk Control on Kid's Sunglasses.
Proceedings of the Engineering Psychology and Cognitive Ergonomics, 2018

2017
Binocular spatial activity and reverse saliency driven no-reference stereopair quality assessment.
Signal Process. Image Commun., 2017

An upper bound for the crossing number of locally twisted cubes.
Ars Comb., 2017

Cooperative spectrum sensing via 2-SPRT Based multiple-model hypothesis testing.
Proceedings of the 11th Asian Control Conference, 2017

2016
A 2-SPRT Based Approach to Multiple-Model Hypothesis Testing for Multi-Distribution Detection.
IEEE Trans. Signal Process., 2016

VLSI supply chain security risks and mitigation techniques: A survey.
Integr., 2016

Achieving k-channel-connectivity with topology control in cognitive radio networks.
Proceedings of the 2016 IEEE/CIC International Conference on Communications in China, 2016

2015
Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Fingerprint-Based Detection and Diagnosis of Malicious Programs in Hardware.
IEEE Trans. Reliab., 2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.
ACM J. Emerg. Technol. Comput. Syst., 2015

A bio-system inspired nonline ar intelligent controller with application to bio-reactor system.
Neurocomputing, 2015

Reconfiguration-Based VLSI Design for Security.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Practical secure and privacy-preserving scheme for value-added applications in VANETs.
Comput. Commun., 2015

Crosstalk-aware signal probability-based dynamic statistical timing analysis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Analysis of the islets-based glucose control system involving the nonlinear glucose-insulin metabolism model.
Proceedings of the IEEE International Conference on Information and Automation, 2015

Multiple-model hypothesis testing using adaptive representative model.
Proceedings of the 18th International Conference on Information Fusion, 2015

Hardware Design and Verification Techniques for Supply Chain Risk Mitigation.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

Multiple-model hypothesis testing based on 2-SPRT.
Proceedings of the American Control Conference, 2015

2014
No-reference image quality assessment based on spatial and spectral entropies.
Signal Process. Image Commun., 2014

Power/ground supply voltage variation-aware delay test pattern generation.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Input-aware statistical timing analysis for VLSI delay test and average design.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Testing, diagnosis and repair methods for NBTI-induced SRAM faults.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Input-aware statistical timing analysis-based delay test pattern generation.
Proceedings of the International Symposium on Quality Electronic Design, 2013

An Improved Identity-Based Batch Verification Scheme for VANETs.
Proceedings of the 2013 5th International Conference on Intelligent Networking and Collaborative Systems, 2013

On the Security of a Privacy-Preserving Key Management Scheme for Location Based Services in VANETs.
Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013

2012
Resilient and adaptive performance logic.
ACM J. Emerg. Technol. Comput. Syst., 2012

Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Minimum logic of guaranteed single soft error resilience based on group distance-two code.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Adaptive Vector Flow for Active Contour Model.
Proceedings of the Pattern Recognition - Chinese Conference, 2012

2011
An Intelligent Bi-Cooperative Decoupling Control Approach Based on Modulation Mechanism of Internal Environment in Body.
IEEE Trans. Control. Syst. Technol., 2011

Statistical full-chip dynamic power estimation considering spatial correlations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel neural network inspired from Neuroendocrine-Immune System.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

An intelligent controller inspired by bi-cooperative modulation mechanism.
Proceedings of the Seventh International Conference on Natural Computation, 2011

2010
Architecture exploration of crossbar-based nanoscale reconfigurable computing platforms.
Nano Commun. Networks, 2010

Voltage-controlled nano-addressing for nanosystem communication.
Nano Commun. Networks, 2010

Intel LVS logic as a combinational logic paradigm in CNT technology.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Error-detecting/correcting-code-based self-checked/corrected/timed circuits.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Reduced Voltage Scaling in Clock Distribution Networks.
VLSI Design, 2009

Energy Efficient Swing signal generation circuits for clock distribution networks.
Proceedings of the IEEE International Conference on Systems, 2009

Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Robust differential asynchronous nanoelectronic circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-Architecture.
Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

A collaborative optimized genetic algorithm based on regulation mechanism of neuroendocrine-immune system.
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation, 2009

Analysis and extraction of parametric variation effects on microelectrofluidics-based biochips.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Voltage Controlled Nano Addressing Circuit.
Proceedings of the Nano-Net - Third International ICST Conference, 2008

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression.
Proceedings of the Design, Automation and Test in Europe, 2008

Signal Probability Based Statistical Timing Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Statistical Timing Analysis in the Presence of Signal-Integrity Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
Proceedings of the 25th International Conference on Computer Design, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Statistical crosstalk aggressor alignment aware interconnect delay calculation.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Constructing Current-Based Gate Models Based on Existing Timing Library.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient decoupling capacitor planning via convex programming methods.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical gate delay calculation with crosstalk alignment consideration.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
A Novel Intelligent Controller Based on Modulation of Neuroendocrine System.
Proceedings of the Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30, 2005

Supply Voltage Degradation Aware Analytical Placement.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Nontree routing for reliability and yield improvement [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On the skew-bounded minimum-buffer routing tree problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002
Toward better wireload models in the presence of obstacles.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Non-tree routing for reliability and yield improvement.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Interconnect implications of growth-based structural models for VLSI circuits.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001


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