Qiyuan Liu

Orcid: 0000-0001-5605-3409

Affiliations:
  • Qualcomm, Tempe, AZ, USA
  • Texas A&M University, College Station, TX, USA (PhD 2017)


According to our database1, Qiyuan Liu authored at least 10 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator.
IEEE J. Solid State Circuits, 2020

2019
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.
IEEE J. Solid State Circuits, 2018

A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques.
IEEE J. Solid State Circuits, 2017

A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 13bit 200MS/S pipeline ADC with current-mode MDACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.
IEEE J. Solid State Circuits, 2016


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