Dadian Zhou

Orcid: 0000-0001-9068-890X

According to our database1, Dadian Zhou authored at least 12 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2021
Recent Advances on Linear Low-Dropout Regulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test.
IEEE Trans. Instrum. Meas., 2020

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier.
IEEE Trans. Circuits Syst., 2020

A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator.
IEEE J. Solid State Circuits, 2020

2019
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.
IEEE J. Solid State Circuits, 2018

2017
A 200MSPS time-interleaved 12-bit ADC system with digital calibration.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 13bit 200MS/S pipeline ADC with current-mode MDACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2012
Brain Storm Optimization Algorithm with Modified Step-Size and Individual Generation.
Proceedings of the Advances in Swarm Intelligence - Third International Conference, 2012


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