Carlos Briseno-Vidrios
Orcid: 0000-0001-7315-4148
According to our database1,
Carlos Briseno-Vidrios
authored at least 9 papers
between 2015 and 2019.
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Bibliography
2019
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
IEEE J. Solid State Circuits, 2018
2017
Low-Power G<sub>m</sub>-C Filter Employing Current-Reuse Differential Difference Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.
IEEE J. Solid State Circuits, 2017
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer.
IEEE J. Solid State Circuits, 2016
2015
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique.
Proceedings of the Symposium on VLSI Circuits, 2015