Santosh Ghosh

Shreyas Sen

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator.

[BibT_eX]

[DOI]

Archisman Ghosh

Jose Maria Bermudo Mera

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.

[BibT_eX]

[DOI]

Harish K. Krishnamurthy

IEEE J. Solid State Circuits, 2021

Where Star Wars Meets Star Trek: SABER and Dilithium on the Same Polynomial Multiplier.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Log-structured Protocols in Delos.

[BibT_eX]

[DOI]

Proceedings of the SOSP '21: ACM SIGOPS 28th Symposium on Operating Systems Principles, 2021

Cryptographic Capability Computing.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

PG-CAS: Patterned-Ground Co-Planar Capacitive Asymmetry Sensing for mm-Range EM Side-Channel Attack Probe Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Constraints for effective distribution network expansion planning: an ample review.

[BibT_eX]

[DOI]

Mandhir Kumar Verma

Vivekananda Mukherjee

Vinod Kumar Yadav

Int. J. Syst. Assur. Eng. Manag., 2020

Towards efficient and automated side-channel evaluations at design time.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2020

Efficient BIKE Hardware Design with Constant-Time Decoder.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Κ-Cipher: A Low Latency, Bit Length Parameterizable Cipher.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Gimli Encryption in 715.9 psec.

[BibT_eX]

[DOI]

Michael E. Kounavis

Sergej Deutsch

IACR Cryptol. ePrint Arch., 2020

SCNIFFER: Low-Cost, Automated, Efficient Electromagnetic Side-Channel Sniffing.

[BibT_eX]

[DOI]

IEEE Access, 2020

Virtual Consensus in Delos.

[BibT_eX]

[DOI]

Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation, 2020

Killing EM Side-Channel Leakage at its Source.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

K-Cipher: A Low Latency, Bit Length Parameterizable Cipher.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Computers and Communications, 2020

HCC: 100 Gbps AES-GCM Encrypted Inline DMA Transfers Between SGX Enclave and FPGA Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Information and Communications Security - 22nd International Conference, 2020

Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

Anonymous Attestation for IoT.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Lightweight Post-Quantum-Secure Digital Signature Approach for IoT Motes.

[BibT_eX]

[DOI]

Rafael Misoczki

Manoj R. Sastry

IACR Cryptol. ePrint Arch., 2019

X-DeepSCA: Cross-Device Deep Learning Side Channel Attack.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Intelligent IoT Motes: Preventing Their Abuse at the Weakest Entry Point.

[BibT_eX]

[DOI]

Rafael Misoczki

Manoj R. Sastry

IEEE Des. Test, 2019

SCNIFFER: Low-Cost, Automated, EfficientElectromagnetic Side-Channel Sniffing.

[BibT_eX]

[DOI]

CoRR, 2019

STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2018

ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Ground-up Root-cause Analysis guided Low-Overhead Generic Countermeasure for Electro-Magnetic Side-Channel Attack.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.

[BibT_eX]

[DOI]

CoRR, 2018

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

A first look at performance of TV streaming sticks.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE Sarnoff Symposium 2017, Newark, NJ, USA, 2017

Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

High efficiency power side-channel attack immunity using noise injection in attenuated signature domain.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016

Shuffling across rounds: A lightweight strategy to counter side-channel attacks.

[BibT_eX]

[DOI]

Sikhar Patranabis

Debapriya Basu Roy

Praveen Kumar Vadnala

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Parsimonious design strategy for linear layers with high diffusion in block ciphers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015

On the Implementation of Unified Arithmetic on Binary Huff Curves.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

2014

BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor.

[BibT_eX]

[DOI]

Ingrid Verbauwhede

IEEE Trans. Computers, 2014

Indian thermal power plant challenges and remedies via application of modified data envelopment analysis.

[BibT_eX]

[DOI]

Int. Trans. Oper. Res., 2014

On the implementation of mceliece with CCA2 indeterminacy by SHA-3.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Security Analysis of Industrial Test Compression Schemes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

First-order DPA Vulnerability of Rijndael: Security and Area-delay Optimization Trade-off.

[BibT_eX]

[DOI]

Int. J. Netw. Secur., 2013

Secure JTAG Implementation Using Schnorr Protocol.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

2012

Scan attacks on side-channel and fault attack resistant public-key implementations.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2012

Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks.

[BibT_eX]

[DOI]

Arpan Mondal

Abhijit Das

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform.

[BibT_eX]

[DOI]

Ingrid Verbauwhede

Proceedings of the Pairing-Based Cryptography - Pairing 2012, 2012

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Fault Attack, Countermeasures on Pairing Based Cryptography.

[BibT_eX]

[DOI]

Int. J. Netw. Secur., 2011

Security of Prime Field Pairing Cryptoprocessor Against Differential Power Attack.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Security of Prime Field Pairing Cryptoprocessor against Differential Power Attack.

[BibT_eX]

[DOI]

Proceedings of the Security Aspects in Information Technology, 2011

High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields.

[BibT_eX]

[DOI]

Abhijit Das

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010

High Speed Flexible Pairing Cryptoprocessor on FPGA Platform.

[BibT_eX]

[DOI]

Proceedings of the Pairing-Based Cryptography - Pairing 2010, 2010

High speed Fp multipliers and adders on FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009

Effect of glitches against masked AES S-box implementation and countermeasure.

[BibT_eX]

[DOI]

IET Inf. Secur., 2009

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2009

2008

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A GF(p) elliptic curve group operator resistant against side channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Toward Memory-efficient Design of Video Encoders for Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Speed-area optimized FPGA implementation for Full Search Block Matching.

[BibT_eX]

[DOI]

Avishek Saha

Proceedings of the 25th International Conference on Computer Design, 2007

A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definition TVs (HDTV).

[BibT_eX]

[DOI]

Avishek Saha

Proceedings of the High Performance Computing, 2007

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An area optimized reconfigurable encryptor for AES-Rijndael.

[BibT_eX]

[DOI]