Ramachandran Vaidyanathan

According to our database1, Ramachandran Vaidyanathan
  • authored at least 72 papers between 1992 and 2017.
  • has a "Dijkstra number"2 of four.

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Bibliography

2017
Estimation of RFID Tag Population Size by Gaussian Estimator.
CoRR, 2017

O(log N)-Time Complete Visibility for Asynchronous Robots with Lights.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Introduction to RAW Workshop.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Combining Boolean Gates and Branching Programs in One Model can Lead to Faster Circuits.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Efficient Totally-Ordered Subset Generation, with Application in Partial Reconfiguration.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Guest Editorial RAW 2014.
TRETS, 2016

Complete Visibility for Robots with Lights in O(1) Time.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2016

EduPar Introduction and Committees.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

RAW Introduction and Committees.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
Asymptotic Error Free Partitioning Over Noisy Boolean Multiaccess Channels.
IEEE Trans. Information Theory, 2015

Partition Information and its Transmission Over Boolean Multi-Access Channels.
IEEE Trans. Information Theory, 2015

Asymptotic Error Free Partitioning over Noisy Boolean Multiaccess Channels.
CoRR, 2015

Efficient transformations for Klee's measure problem in the streaming model.
Comput. Geom., 2015

Detection of graph structures via communications over a multiaccess Boolean channel.
Proceedings of the IEEE International Symposium on Information Theory, 2015

Logarithmic-Time Complete Visibility for Robots with Lights.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

RAW Introduction and Committees.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

An Architecture for Configuring an Effcient Scan Path for a Subset of Elements.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2014
Partition Information and its Transmission over Boolean Multi-Access Channels.
CoRR, 2014

Achievable partition information rate over noisy multi-access Boolean channel.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014

RAW Introduction and Committees.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Work-Efficient Load Balancing.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

Transmission of partitioning information over non-adaptive multi-access Boolean channel.
Proceedings of the 48th Annual Conference on Information Sciences and Systems, 2014

2013
Pipelined Execution of Windowed Image Computations.
IJNC, 2013

RAW Introduction.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
On Running Windowed Image Computations on a Pipeline.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

An Efficient Transformation for the Klee's Measure Problem in the Streaming Model.
Proceedings of the 24th Canadian Conference on Computational Geometry, 2012

2010
MU-decoders: A class of fast and efficient configurable decoders.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2008
Configurable decoders with application in fast partial reconfiguration of FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm.
Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008

2007
Dynamic Reconfiguration on the R-Mesh.
Proceedings of the Handbook of Parallel Computing - Models, Algorithms and Applications., 2007

2006
Routing Multiple Width Communications on the Circuit Switched Tree.
Int. J. Found. Comput. Sci., 2006

Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005
Configuring the Circuit Switched Tree for Multiple Width Communications.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

On Mapping Multidimensional Weak Tori on Optical Slab Waveguides.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

2004
Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms.
IEEE Trans. Computers, 2004

The Mesh With Binary Tree Networks: An Enhanced Mesh With Low Bus-Loading.
Journal of Interconnection Networks, 2004

2003
Degree of scalability: scalable reconfigurable mesh algorithms for multiple addition and matrix-vector multiplication.
Parallel Computing, 2003

On Designing Implementable Algorithms for the Linear Reconfigurable Mesh.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Fault Tolerance in Multiple Bus Networks with Unbalanced Resource Utilization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Adaptive Image Filtering Using Run-Time Reconfiguration.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Using Bus Linearization to Scale the Reconfigurable Mesh.
J. Parallel Distrib. Comput., 2002

Scaling multiple addition and prefix sums on the reconfigurable mesh.
Inf. Process. Lett., 2002

Reconfigurable Mesh on the Reconfigurable Tree Array.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Free Space All-optical Crossconnect.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

On the Communication Capability of the Self-Reconfigurable Gate Array Architecture.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2000
Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses.
J. Parallel Distrib. Comput., 2000

1999
Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Improved Scaling Simulation of the General Reconfigurable Mesh.
Proceedings of the Parallel and Distributed Processing, 1999

High Speed, High Capacity Bused Interconnects using Optical Slab Waveguides.
Proceedings of the Parallel and Distributed Processing, 1999

Lower Bounds on the Loading of Degree-2 Multiple Bus Networks for Binary-Tree Algorithms.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1998
Scaling Simulation of the Fusing-Restricted Reconfigurable Mesh.
IEEE Trans. Parallel Distrib. Syst., 1998

Tighter and Broader Complexity Results for Reconfigurable Models.
Parallel Processing Letters, 1998

1997
Constant Time Graph Algorithms on the Reconfigurable Mutliple Buss Machine.
J. Parallel Distrib. Comput., 1997

A Scalable and Efficient Algorithm for Computing the City Block Distance Transform on Reconfigurable Meshes.
Comput. J., 1997

An Optimal Multiple Bus Network for Fan-in Algorithms.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple Bus Networks.
IEEE Trans. Parallel Distrib. Syst., 1996

On the Power of Segmenting and Fusing Buses.
J. Parallel Distrib. Comput., 1996

The Bus-Connected Ringed Tree: A Versatile Interconnection Network.
J. Parallel Distrib. Comput., 1996

Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms.
Proceedings of IPPS '96, 1996

Integer and Floating Point Matrix-Vector Multiplication on the Reconfigurable Mesh.
Proceedings of IPPS '96, 1996

1995
Bus-Based Networks for Fan-In and Uniform Hypercube Algorithms.
Parallel Computing, 1995

Parallel Integer Sorting Using Small Operations.
Acta Inf., 1995

1994
Constant Time Graph and Poset Algorithms on the Reconfigurable Multiple Bus Machine.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Optimal Simulation of Multidimensional Reconfigurable Meshes by Two-Dimensional Reconfigurable Meshes.
Inf. Process. Lett., 1993

Running ASCEND, DESCEND and PIPELINE Algorithms in Parallel Using Small Processors.
Inf. Process. Lett., 1993

Towards Optimal Parallel Radix Sorting.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

On the Power of Segmenting and Fusing Buses.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

List Ranking and Graph Algorithms on the Reconfigurable Multiple Bus Machine.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Bus-Based Tree Structures for Efficient Parallel Computation.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

A potential-driven approach to constructing rectilinear Steiner trees.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
PRAMs with Variable Word-Size.
Inf. Process. Lett., 1992

Sorting on PRAMs with Reconfigurable Buses.
Inf. Process. Lett., 1992


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