Craig B. Stunkel

According to our database1, Craig B. Stunkel authored at least 41 papers between 1988 and 2016.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2016
An Evaluation of Network Architectures for Next Generation Supercomputers.
Proceedings of the 7th International Workshop on Performance Modeling, 2016

Space Performance Tradeoffs in Compressing MPI Group Data Structures.
Proceedings of the 23rd European MPI Users' Group Meeting, EuroMPI 2016, 2016

2012
Special issue on Communication Architectures for Scalable Systems.
J. Parallel Distrib. Comput., 2012

2011
CASS Introduction.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Welcome to CAC/SSPS 2010.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2008
Interconnection Networks for Parallel Computers.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

2007
Harnessing massive parallelism in the era of parallelism for the masses.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2005
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Improved Point-to-Point and Collective Communication Performance with Output-Queued High-Radix Routers.
Proceedings of the High Performance Computing, 2005

2004
What are the future trends in high-performance inter.connects for parallel computers? [Panel 1].
Proceedings of the 12th Annual IEEE Symposium on High Performance Interconnects, 2004

2002
HIPIQS: A High-Performance Switch Architecture Using Input Queuing.
IEEE Trans. Parallel Distrib. Syst., 2002

Workshop Introduction.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Architectural Support for Efficient Multicasting in Irregular Networks.
IEEE Trans. Parallel Distrib. Syst., 2001

Adaptive Routing on the New Switch Chip for IBM SP Systems.
J. Parallel Distrib. Comput., 2001

2000
Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact.
IEEE Trans. Parallel Distrib. Syst., 2000

Adaptive Routing in RS/6000 SP-Like Bidirectional Multistage Interconnection Networks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

1999
A New Switch Chip for IBM RS/6000 SP Systems.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

1998
Efficient Broadcast and Multicast on Multistage Interconnection Networks Using Multiport Encoding.
IEEE Trans. Parallel Distrib. Syst., 1998

HIPIQS: A High-Performance Switch Architecture Using Input Queuing.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Where to Provide Support for Efficient Multicasting in Irregular Networks: Network Interface or Switch?
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

IBM RS/6000 SP Interconnection Network Topologies for Large Systems.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

Convergence Points on Commercial Parallel Systems: Do We Have the Node Architecture? Do We Have the Network? Do We Have the Programming Paradigm?
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1997
Clock Synchronization on a Multicomputer.
J. Parallel Distrib. Comput., 1997

Challenges in the Design of Contemporary Routers.
Proceedings of the Parallel Computer Routing and Communication, 1997

Multicasting in Irregular Networks with Cut-Through Switches Using Tree-Based Multidestination Worms.
Proceedings of the Parallel Computer Routing and Communication, 1997

Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their Impact.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

A Reliable Hardware Barrier Synchronization Scheme.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996
Efficient broadcast and multicast on multistage interconnection networks using multiport encoding.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Adaptive Source Routing in Multistage Interconnection Networks.
Proceedings of IPPS '96, 1996

Commercially Viable MPP Networks.
Proceedings of the 1996 International Conference on Parallel Processing Workshop, 1996

1995
The SP2 High-Performance Switch.
IBM Systems Journal, 1995

Time synchronization on SP1 and SP2 parallel systems.
Proceedings of IPPS '95, 1995

1994
Architecture and Implementation of Vulcan.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

Sp2 high-performance switch architecture.
Proceedings of the Hot Interconnects II, 1994

1992
An Analysis of Cache Performance for a Hypercube Multicomputer.
IEEE Trans. Parallel Distrib. Syst., 1992

Address tracing of parallel systems via TRAPEDS.
Microprocessors and Microsystems - Embedded Hardware Design, 1992

1991
Address Tracing for Parallel Machines.
IEEE Computer, 1991

1990
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor.
IEEE Trans. Computers, 1990

1989
TRAPEDS: Producing Traces for Multicomputers Via Execution Driven Simulation.
Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1989

Analysis of Hypercube Cache Performance Using Address Traces Generated by TRAPEDS.
Proceedings of the International Conference on Parallel Processing, 1989

1988
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988


  Loading...