Ramprasath Srinivasa Gopalakrishnan

Orcid: 0000-0001-9487-9340

Affiliations:
  • University of Minnesota, Minneapolis, MN, USA (2020-2023)
  • Indian Institute of Technology Madras, Department of Electrical Engineering, India (PhD 2016)


According to our database1, Ramprasath Srinivasa Gopalakrishnan authored at least 16 papers between 2012 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization.
Dataset, January, 2024

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Reinforcing the Connection between Analog Design and EDA (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.
ACM Trans. Design Autom. Electr. Syst., September, 2023

3SAT on an All-to-All-Connected CMOS Ising Solver Chip.
CoRR, 2023

A Multicore GNN Training Accelerator.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

GNNIE: GNN inference engine with load-balancing and graph-specific caching.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2016
A Skew-Normal Canonical Model for Statistical Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient.
ACM Trans. Design Autom. Electr. Syst., 2016

2015
An efficient algorithm for statistical timing yield optimization.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Statistical Criticality Computation Using the Circuit Delay.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012
On the computation of criticality in statistical timing analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012


  Loading...