Sarvesh Bhardwaj
According to our database1,
Sarvesh Bhardwaj
authored at least 30 papers
between 2002 and 2020.
Collaborative distances:
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Bibliography
2020
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2010
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
IEEE Trans. Veh. Technol., 2009
2008
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory.
J. Low Power Electron., 2008
Scalable model for predicting the effect of negative bias temperature instability for reliable design.
IET Circuits Devices Syst., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
2007
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.
J. Low Power Electron., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Stochastic variational analysis of large power grids considering intra-die correlations.
Proceedings of the 43rd Design Automation Conference, 2006
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Leakage minimization of nano-scale circuits in the presence of systematic and random variations.
Proceedings of the 42nd Design Automation Conference, 2005
An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002