Robert de Simone

According to our database1, Robert de Simone authored at least 78 papers between 1984 and 2018.

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Bibliography

2018
Beyond Time-Triggered Co-simulation of Cyber-Physical Systems for Performance and Accuracy Improvements.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

Time in SCCharts.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

2017
Explicit Control of Dataflow Graphs with MARTE/CCSL.
Proceedings of the 5th International Conference on Model-Driven Engineering and Software Development, 2017

2016
Instant-Based and State-Based Analysis of Infinite Logical Clock.
Proceedings of the Structured Object-Oriented Formal Language and Method, 2016

Divergence Detection for CCSL Specification via Clock Causality Chain.
Proceedings of the Dependable Software Engineering: Theories, Tools, and Applications, 2016

Keynote talk II: Multiform logical time for Me/Mo-codesign.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Using SystemC Cyber Models in an FMI Co-Simulation Environment: Results and Proposed FMI Enhancements.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core Architectures.
ACM Trans. Embedded Comput. Syst., 2015

Correctness issues on MARTE/CCSL constraints.
Sci. Comput. Program., 2015

Efficient FFT mapping on GPU for radar processing application: modeling and implementation.
CoRR, 2015

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2015

2014
Reconciling performance and predictability on a many-core through off-line mapping.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Execution of heterogeneous models for thermal analysis with a multi-view approach.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
Explicit routing schemes for implementation of cellular automata on processor arrays.
Natural Computing, 2013

Safe CCSL specifications and marked graphs.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Schedulability Analysis with CCSL Specifications.
Proceedings of the 20th Asia-Pacific Software Engineering Conference, 2013

2012
Periodic scheduling of marked graphs using balanced binary words.
Theor. Comput. Sci., 2012

Periodic scheduling of marked graphs using balanced binary words
CoRR, 2012

Programmable routers for efficient mapping of applications onto NoC-based MPSoCs.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Logical time: specification vs. implementation.
ACM SIGSOFT Software Engineering Notes, 2011

From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations.
Fundam. Inform., 2011

2010
Introduction to special issue: papers from UML&FM'2009.
ISSE, 2010

The clock constraint specification language for building timed causality models - Application to synchronous data flow graphs.
ISSE, 2010

Polychronous Analysis of Timing Constraints in UML MARTE.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations.
Proceedings of the Synthesis of Embedded Software, 2010

Formal Modeling of Embedded Systems with Explicit Schedules and Routes.
Proceedings of the Synthesis of Embedded Software, 2010

The Time Model of Logical Clocks Available in the OMG MARTE Profile.
Proceedings of the Synthesis of Embedded Software, 2010

2009
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell.
Electr. Notes Theor. Comput. Sci., 2009

IP-XACT components with abstract time characterization.
Proceedings of the Forum on specification and Design Languages, 2009

Clock-driven distributed real-time implementation of endochronous synchronous programs.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

Synchronous Hypothesis and Polychronous Languages.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Preface.
Electr. Notes Theor. Comput. Sci., 2008

MARTE: a profile for RT/E systems modeling, analysis-and simulation?
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Dealing with AADL End-to-End Flow Latency with UML MARTE.
Proceedings of the 13th International Conference on Engineering of Complex Computer Systems (ICECCS 2008), March 31 2008, 2008

Event-Triggered vs. Time-Triggered Communications with UML MARTE.
Proceedings of the Forum on specification and Design Languages, 2008

MARTE vs. AADL for Discrete-Event and Discrete-Time Domains.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

2007
Formal Methods for Scheduling of Latency-Insensitive Designs.
EURASIP J. Emb. Sys., 2007

Modeling Time(s).
Proceedings of the Model Driven Engineering Languages and Systems, 2007

MARTE: Also an UML Profile for Modeling AADL Applications.
Proceedings of the 12th International Conference on Engineering of Complex Computer Systems (ICECCS 2007), 2007

Time Modeling in MARTE.
Proceedings of the Forum on specification and Design Languages, 2007

Modeling of immediate vs. delayed data communications: from AADL to UML Marte.
Proceedings of the Forum on specification and Design Languages, 2007

Necessary and sufficient conditions for deterministic desynchronization.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

2006
Towards a "Synchronous Reactive" UML profile?
STTT, 2006

Syntax-driven optimisations for reachable state space construction of ESTEREL programs.
IJES, 2006

Syntax-driven Behavior Partitioning for Model-checking of Esterel Programs.
Electr. Notes Theor. Comput. Sci., 2006

Another Glance at Relay Stations in Latency-Insensitive Design.
Electr. Notes Theor. Comput. Sci., 2006

Latency-insensitive design and central repetitive scheduling.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

2005
The Synchronous Hypothesis and Synchronous Languages.
Proceedings of the Embedded Systems Handbook., 2005

Loops in esterel.
ACM Trans. Embedded Comput. Syst., 2005

Guidelines for a graduate curriculum on embedded software and systems.
ACM Trans. Embedded Comput. Syst., 2005

P2I: An Innovative MDA Methodology for Embedded Real-Time System.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Syntax-Driven Reachable State Space Construction of Synchronous Reactive Programs.
Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2004
Curing schizophrenia by program rewriting in Esterel.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

2003
The synchronous languages 12 years later.
Proceedings of the IEEE, 2003

Instantaneous Termination in Pure Esterel.
Proceedings of the Static Analysis, 10th International Symposium, 2003

Optimizations for Faster Execution of Esterel Programs.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

2002
Ninth International Conference on Concurrency Theory 1998 - Editorial.
Theor. Comput. Sci., 2002

2000
ESTEREL: a formal method applied to avionic software development.
Sci. Comput. Program., 2000

1996
The SL Synchronous Language.
IEEE Trans. Software Eng., 1996

Automated design of communication protocols using ESTEREL.
J. High Speed Networks, 1996

The FC2TOOLS Set (Tool Demonstration).
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1996

Verifying Synchronous Reactive Systems Programmed in ESTEREL.
Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1996

The FC2TOOLS Set.
Proceedings of the Algebraic Methodology and Software Technology, 1996

1995
Using PO Methods for Verfying Behavioural Equivalences.
Proceedings of the Formal Description Techniques VIII, 1995

1994
Model-Based Verification Methods and Tools (Abstract).
Proceedings of the CONCUR '94, 1994

Compositional Semantics of ESTEREL and Verification by Compositional Reductions.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1992
Auto/Autograph.
Formal Methods in System Design, 1992

Symbolic Bisimulation Minimisation.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991
Causal Models for Rational Algebraic Processes.
Proceedings of the CONCUR '91, 1991

1990
Auto/Autograph.
Proceedings of the Computer-Aided Verification, 1990

1989
Process Calculi, from Theory to Practice: Verification Tools.
Proceedings of the Automatic Verification Methods for Finite State Systems, 1989

1985
Higher-Level Synchronising Devices in Meije-SCCS.
Theor. Comput. Sci., 1985

Petri Nets and Algebraic Calculi of Processes.
Proceedings of the STACS 85, 1985

1984
Langages Infinitaires et Produit de Mixage.
Theor. Comput. Sci., 1984

On Meije and SCCS: Infinite Sum Operators VS. Non-Guarded Definitions.
Theor. Comput. Sci., 1984


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