Ronald P. Luijten

According to our database1, Ronald P. Luijten authored at least 26 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Objective, innovation and impact of the energy-efficient dome microdatacenter.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

A Record-Setting Microserver: A Data-Centre in a Shoebox.
ERCIM News, 2015

4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Power measurements and cooling of the DOME 28nm 1.8GHz 24-thread ppc64 μServer compute node.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dual function heat-spreading and performance of the IBM/ASTRON DOME 64-bit μServer demonstrator.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Holistic power analysis of implementation alternatives for a very large scale synthesis array with phased array stations.
Proceedings of the IEEE International Conference on Acoustics, 2014

The DOME embedded 64 bit microserver demonstrator.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

The Network Adapter: The Missing Link between MPI Applications and Network Performance.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Pinned to the walls: impact of packaging and application properties on the memory and power walls.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

On the optimum switch radix in fat tree networks.
Proceedings of the 12th IEEE International Conference on High Performance Switching and Routing, 2011

Optimization of link bandwidth for parallel communication performance.
Proceedings of the 28th International Performance Computing and Communications Conference, 2009

Oblivious routing schemes in extended generalized Fat Tree networks.
Proceedings of the 2009 IEEE International Conference on Cluster Computing, August 31, 2009

Lightspeed Communications in Supercomputers.
ERCIM News, 2008

Design issues in next-generation merchant switch fabrics.
IEEE/ACM Trans. Netw., 2007

Designing a Crossbar Scheduler for HPC Applications.
IEEE Micro, 2006

Viable opto-electronic HPC interconnect fabrics.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times.
IEEE Micro, 2003

Stability degree of switches with finite buffers and non-negligible round-trip time.
Microprocessors and Microsystems, 2003

Flow control scheduling.
Microprocessors and Microsystems, 2003

Current issues in packet switch design.
Computer Communication Review, 2003

Reducing memory size in buffered crossbars with large internal flow control latency.
Proceedings of the Global Telecommunications Conference, 2003

Stability of CIOQ switches with finite buffers and non-negligible round-trip time.
Proceedings of the 11th International Conference on Computer Communications and Networks, 2002

Optimizing flow control for buffered switches.
Proceedings of the 11th International Conference on Computer Communications and Networks, 2002

A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support.
Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

Shared memory switching + virtual output queuing: A robust and scalable switch.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Optimized architecture and design of an output-queued CMOS switch chip.
Proceedings of the 10th International Conference on Computer Communications and Networks, 2001