Christoph Hagleitner

According to our database1, Christoph Hagleitner authored at least 65 papers between 2003 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
FPGA Accelerated Analysis of Boolean Gene Regulatory Networks.
IEEE ACM Trans. Comput. Biol. Bioinform., 2020

The IBM 4769 Cryptographic Coprocessor.
IBM J. Res. Dev., 2020

PHRYCTORIA: A Messaging System for Transprecision OpenCAPI-attached FPGA Accelerators.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

High Bandwidth Memory on FPGAs: A Data Analytics Perspective.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2019
Low Precision Processing for High Order Stencil Computations.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Near-Memory Acceleration for Radio Astronomy.
IEEE Trans. Parallel Distributed Syst., 2018

A hardware compilation framework for text analytics queries.
J. Parallel Distributed Comput., 2018

A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping.
Proceedings of the International Conference on Field-Programmable Technology, 2018

ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017
An Architecture for Integrated Near-Data Processors.
ACM Trans. Archit. Code Optim., 2017

Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing.
Proceedings of the 46th International Conference on Parallel Processing, 2017

An FPGA Platform for Hyperscalers.
Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

Accelerated analysis of Boolean gene regulatory networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Sorting big data on heterogeneous near-data processing systems.
Proceedings of the Computing Frontiers Conference, 2017

2016
Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT.
J. Signal Process. Syst., 2016

A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware.
Sustain. Comput. Informatics Syst., 2016

Exploring the Design Space of an Energy-Efficient Accelerator for the SKA1-Low Central Signal Processor.
Int. J. Parallel Program., 2016

Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Network-attached FPGAs for data center applications.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Annotation-based finite-state transducers on reconfigurable devices.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gates.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Disaggregated FPGAs: Network Performance Comparison against Bare-Metal Servers, Virtual Machines and Linux Containers.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

An architecture for near-data processing systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Challenges in exascale radio astronomy: Can the SKA ride the technology wave?
Int. J. High Perform. Comput. Appl., 2015

Enabling FPGAs in Hyperscale Data Centers.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

Ultra-low-energy adiabatic dynamic logic circuits using nanoelectromechanical switches.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Accelerating arithmetic kernels with coherent attached FPGA coprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An energy-efficient custom architecture for the SKA1-low central signal processor.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Energy and Latency Optimization in NEM Relay-Based Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Giving Text Analytics a Boost.
IEEE Micro, 2014

Exascale Radio Astronomy: Can We Ride the Technology Wave?
Proceedings of the Supercomputing - 29th International Conference, 2014

Hardware-accelerated text analytics.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

A 6.7 MHz nanoelectromechanical ring oscillator using curved cantilever switches coated with amorphous carbon.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Exploring the design space of programmable regular expression matching accelerators.
J. Syst. Archit., 2013

Wire-Speed Regular-Expression Scanning at 20 Gbit/s and Beyond.
ERCIM News, 2013

Modelling NEM relays for digital circuit applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Token-based dictionary pattern matching for text analytics.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Hardware-accelerated regular expression matching for high-throughput text analytics.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Session 11 overview: Sensors and MEMS: Imagers, MEMS, medical and displays subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Rx Stack Accelerator for 10 GbE Integrated NIC.
Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

Proving correctness of regular expression accelerators.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Fusion of MEMS and circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Memory-efficient distribution of regular expressions for fast deep packet inspection.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Probe-based ultrahigh-density storage technology.
IBM J. Res. Dev., 2008

2007
Modeling, Design, and Verification for the Analog Front-End of a MEMS-Based Parallel Scanning-Probe Storage Device.
IEEE J. Solid State Circuits, 2007

A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Signal processing for probe storage.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring.
Proceedings of the 2004 Design, 2004

2003

Interface circuitry for CMOS-based monolithic gas sensor arrays.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A micro-hotplate-based monolithic CMOS gas sensor array.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


  Loading...