Ross M. Walker

Affiliations:
  • University of Utah, Salt Lake City, UT, USA


According to our database1, Ross M. Walker authored at least 11 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2021
A 250-600 MHz Ring Oscillator-Based Phase-Locked Loop for Implantable Wireline Applications, Using 1.0 V Supply in 180 nm CMOS.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

2020
A Multiplexed Electrochemical Measurement System for Characterization of Implanted Electrodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Verification of a Rapidly Multiplexed Circuit for Scalable Action Potential Recording.
IEEE Trans. Biomed. Circuits Syst., 2019

Design of a 180 nm CMOS transceiver for implantable wireline communication, achieving 800 Mbps at BER<1e-12 with 22.4 dB of channel loss.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
IEEE Micro, 2018

A Compact, Low-Noise, Chopped Front-End for Peripheral Nerve Recording in 180 nm CMOS.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

High-Speed Communication Up to 600 Mbps Over FDA-Cleared implantable Wirelines.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Integrated neural interfaces.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.
Proceedings of the 17th Latin-American Test Symposium, 2016

Digital, analog and RF design opportunities of three-independent-gate transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2012
HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2012


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