Naveen Muralimanohar

IEEE Micro, 2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.

[BibT_eX]

[DOI]

Anirban Nag

Ali Shafiee

Vivek Srikumar

CoRR, 2018

2017

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.

[BibT_eX]

[DOI]

Karthikeyan Sankaralingam

ACM Trans. Archit. Code Optim., 2017

2016

Near-Memory Data Services.

[BibT_eX]

[DOI]

Cristian Estan

IEEE Micro, 2016

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.

[BibT_eX]

[DOI]

Ali Shafiee

Anirban Nag

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.

[BibT_eX]

[DOI]

Robert Schreiber

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Improving memristor memory with sneak current sharing.

[BibT_eX]

[DOI]

Manjunath Shevgoor

Yoocharn Jeon

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.

[BibT_eX]

[DOI]

Cong Xu

Dimin Niu

Tao Zhang

Shimeng Yu

Yuan Xie

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

2013

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Understanding the trade-offs in multi-level cell ReRAM memory design.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism.

[BibT_eX]

[DOI]

Doe Hyun Yoon

Parthasarathy Ranganathan

Jichuan Chang

Mattan Erez

IEEE Micro, 2012

Optical High Radix Switch Design.

[BibT_eX]

[DOI]

IEEE Micro, 2012

Design trade-offs for high density cross-point resistive memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

BOOM: Enabling mobile memory based low-power server DIMMs.

[BibT_eX]

[DOI]

Doe Hyun Yoon

Jichuan Chang

Parthasarathy Ranganathan

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.

[BibT_eX]

[DOI]

Niladrish Chatterjee

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Multi-Core Cache Hierarchies

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01734-6, 2011

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2011

System implications of memory reliability in exascale computing.

[BibT_eX]

[DOI]

Proceedings of the Conference on High Performance Computing Networking, 2011

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

The role of optics in future high radix switch design.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

FREE-p: Protecting non-volatile memory against both hard and soft errors.

[BibT_eX]

[DOI]

Doe Hyun Yoon

Parthasarathy Ranganathan

Jichuan Chang

Mattan Erez

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study.

[BibT_eX]

[DOI]

Jung Ho Ahn

Raymond G. Beausoleil

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.

[BibT_eX]

[DOI]

Proceedings of the Conference on High Performance Computing Networking, 2010

Rethinking DRAM design and organization for energy-constrained multi-cores.

[BibT_eX]

[DOI]

Niladrish Chatterjee

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Towards scalable, energy-efficient, bus-based on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

Wire Aware Cache Architecture.

[BibT_eX]

PhD thesis, 2009

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.

[BibT_eX]

[DOI]

Ravishankar R. Iyer

Srihari Makineni

Donald Newell

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Non-uniform power access in large caches with low-swing wires.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High Performance Computing, 2009

2008

Architecting Efficient Interconnects for Large Caches with CACTI 6.0.

[BibT_eX]

[DOI]

IEEE Micro, 2008

Scalable and reliable communication for hardware transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Interconnect design considerations for large NUCA caches.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006

Leveraging Wire Properties at the Microarchitecture Level.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.

[BibT_eX]

[DOI]

Karthik Ramani

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Interconnect-Aware Coherence Protocols for Chip Multiprocessors.

[BibT_eX]

[DOI]

Liqun Cheng

Karthik Ramani

John B. Carter

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.

[BibT_eX]

[DOI]