Ramprasath Srinivasa Gopalakrishnan

According to our database, Ramprasath Srinivasa Gopalakrishnan authored at least 14 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization.

Hüsrev Cilasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanasse, Megan Tan, Mohammad Anees, Ramprasath S, Abhimanyu Kumar, Sachin S. Sapatnekar, Chris H. Kim, Ulya R. Karpuzcu

Dataset, January, 2024

2023

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching.

Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.

Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., September, 2023

3SAT on an All-to-All-Connected CMOS Ising Solver Chip.

M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar

CoRR, 2023

A Multicore GNN Training Accelerator.

Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.

Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.

Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

GNNIE: GNN inference engine with load-balancing and graph-specific caching.

Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2016

A Skew-Normal Canonical Model for Statistical Static Timing Analysis.

Ramprasath S, Madiwalar Vijaykumar, Vinita Vasudevan

IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient.

Ramprasath S, Vinita Vasudevan

ACM Trans. Design Autom. Electr. Syst., 2016

2015

An efficient algorithm for statistical timing yield optimization.

S. Ramprasath, Vinita Vasudevan

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Statistical Criticality Computation Using the Circuit Delay.

S. Ramprasath, Vinita Vasudevan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012

On the computation of criticality in statistical timing analysis.

S. Ramprasath, Vinita Vasudevan

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012