Saeed Shamshiri

According to our database, Saeed Shamshiri authored at least 14 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Comprehensive online defect diagnosis in on-chip networks.

Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems.

Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip.

Saeed Shamshiri, Kwang-Ting (Tim) Cheng

IEEE Trans. Computers, 2011

End-to-end error correction and online diagnosis for on-chip networks.

Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy.

Saeed Shamshiri, Kwang-Ting Cheng

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs.

Saeed Shamshiri, Kwang-Ting Cheng

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Yield and Cost Analysis of a Reliable NoC.

Saeed Shamshiri, Kwang-Ting Cheng

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

A Cost Analysis Framework for Multi-core Systems with Spares.

Saeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng

Proceedings of the 2008 IEEE International Test Conference, 2008

2005

Instruction-level test methodology for CPU core self-testing.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

ACM Trans. Design Autom. Electr. Syst., 2005

Genetic-algorithm Memory Minimisation for Designing Reconfigurable Ip Address Lookup Engine.

Saeed Shamshiri, Seid Mehdi Fakhraie

Int. J. Comput. Intell. Appl., 2005

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.

Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.

Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Instruction level test methodology for CPU core software-based self-testing.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004