Hadi Esmaeilzadeh

IEEE Micro, 2022

Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Accelerating attention through gradient-based learned runtime pruning.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Glimpse: mathematical embedding of hardware specification for neural compilation.

[BibT_eX]

[DOI]

Byung Hoon Ahn

Sean Kinzer

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Conscious AI.

[BibT_eX]

[DOI]

Reza Vaezi

CoRR, 2021

Not All Features Are Equal: Discovering Essential Features for Preserving Prediction Privacy.

[BibT_eX]

[DOI]

Proceedings of the WWW '21: The Web Conference 2021, 2021

VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis.

[BibT_eX]

[DOI]

Ziqing Zeng

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Computational Stack for Cross-Domain Acceleration.

[BibT_eX]

[DOI]

Sean Kinzer

Joon Kyung Kim

Soroush Ghodrati

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

ReLeQ : A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks.

[BibT_eX]

[DOI]

Amir Yazdanbakhsh

IEEE Micro, 2020

Privacy in Deep Learning: A Survey.

[BibT_eX]

[DOI]

CoRR, 2020

A Principled Approach to Learning Stochastic Representations for Privacy in Deep Neural Inference.

[BibT_eX]

[DOI]

CoRR, 2020

Gradient-Based Deep Quantization of Neural Networks through Sinusoidal Adaptive Regularization.

[BibT_eX]

[DOI]

Tarek Elgindi

Charles-Alban Deledalle

CoRR, 2020

Ordering Chaos: Memory-Aware Scheduling of Irregularly Wired Neural Networks for Edge Devices.

[BibT_eX]

[DOI]

Proceedings of Machine Learning and Systems 2020, 2020

Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Divide and Conquer: Leveraging Intermediate Feature Representations for Quantized Training of Neural Networks.

[BibT_eX]

[DOI]

Ahmed Taha Elthakeb

Fatemeh Mireshghallah

Alexander Cloninger

Proceedings of the 37th International Conference on Machine Learning, 2020

Chameleon: Adaptive Code Optimization for Expedited Deep Neural Network Compilation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

Bit-Parallel Vector Composability for Neural Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Shredder: Learning Noise Distributions to Protect Inference Privacy.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

Machine Learning Acceleration.

[BibT_eX]

[DOI]

Jongse Park

IEEE Micro, 2019

Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic.

[BibT_eX]

[DOI]

CoRR, 2019

Divide and Conquer: Leveraging Intermediate Feature Representations for Quantized Training of Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2019

Reinforcement Learning and Adaptive Sampling for Optimized DNN Compilation.

[BibT_eX]

[DOI]

Byung Hoon Ahn

CoRR, 2019

Shredder: Learning Noise to Protect Privacy with Partial DNN Inference on the Edge.

[BibT_eX]

[DOI]

CoRR, 2019

SinReQ: Generalized Sinusoidal Regularization for Automatic Low-Bitwidth Deep Quantized Training.

[BibT_eX]

[DOI]

CoRR, 2019

AxMemo: hardware-compiler co-design for approximate code memoization.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Towards Breaking the Memory Bandwidth Wall Using Approximate Value Prediction.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

In-RDBMS Hardware Acceleration of Advanced Analytics.

[BibT_eX]

[DOI]

Proc. VLDB Endow., 2018

SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning.

[BibT_eX]

[DOI]

IEEE Micro, 2018

ReLeQ: A Reinforcement Learning Approach for Deep Quantization of Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks.

[BibT_eX]

[DOI]

CoRR, 2018

A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

RoboX: An End-to-End Solution to Accelerate Autonomous Control in Robotics.

[BibT_eX]

[DOI]

Jacob Sacks

Divya Mahajan

Richard Connor Lawson

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

In-DRAM near-data approximate acceleration for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

AxBench: A Multiplatform Benchmark Suite for Approximate Computing.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2017

Scale-out acceleration for machine learning.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants.

[BibT_eX]

[DOI]

Hyoukjun Kwon

William Harris

Proceedings of the 30th IEEE Computer Security Foundations Symposium, 2017

2016

RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Mitigating the Memory Bottleneck With Approximate Load Value Prediction.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

From high-level deep neural models to FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

TABLA: A unified template-based framework for accelerating statistical machine learning.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

AxGames: Towards Crowdsourcing Quality Target Determination in Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

Error correction for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Allerton Conference on Communication, 2016

The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.

[BibT_eX]

[DOI]

IEEE Micro, 2015

Axilog: Abstractions for Approximate Hardware Design and Reuse.

[BibT_eX]

[DOI]

Anandhavel Nagendrakumar

Abbas Rahimi

Kia Bazargan

IEEE Micro, 2015

FlexJava: language support for safe and modular approximate programming.

[BibT_eX]

[DOI]

Proceedings of the 2015 10th Joint Meeting on Foundations of Software Engineering, 2015

Neural acceleration for GPU throughput processors.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

SNNAP: Approximate computing on programmable SoCs via neural acceleration.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Axilog: language support for approximate hardware design.

[BibT_eX]

[DOI]

Anandhavel Nagendrakumar

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate acceleration: A path through the era of dark silicon and big data.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

2014

General-purpose code acceleration with limited-precision analog computation.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Rollback-free value prediction with approximate loads.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Approximate Acceleration for a Post Multicore Era.

[BibT_eX]

[DOI]

PhD thesis, 2013

Neural Acceleration for General-Purpose Approximate Programs.

[BibT_eX]

[DOI]

IEEE Micro, 2013

Multicore Model from Abstract Single Core Inputs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2013

Power challenges may end the multicore era.

[BibT_eX]

[DOI]

Commun. ACM, 2013

How to implement effective prediction and forwarding for fusable dynamic multicore architectures.

[BibT_eX]

[DOI]

Behnam Robatmili

Dong Li

Madhu Saravana Sibi Govindan

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Power Limitations and Dark Silicon Challenge the Future of Multicore.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2012

What is Happening to Power, Performance, and Software?

[BibT_eX]

[DOI]

IEEE Micro, 2012

Dark Silicon and the End of Multicore Scaling.

[BibT_eX]

[DOI]

IEEE Micro, 2012

Looking back and looking forward: power, performance, and upheaval.

[BibT_eX]

[DOI]

Commun. ACM, 2012

Architecture support for disciplined approximate programming.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011

Looking back on the language and hardware revolutions: measured power, performance, and scaling.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2006

A parameterized graph-based framework for high-level test synthesis.

[BibT_eX]

[DOI]

Saeed Safari

Amir-Hossein Jahangir

Integr., 2006

Neural network stream processing core (NnSP) for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DCim++: a C++ library for object oriented hardware design and distributed simulation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Instruction-level test methodology for CPU core self-testing.

[BibT_eX]

[DOI]

Saeed Shamshiri

Zainalabedin Navabi

ACM Trans. Design Autom. Electr. Syst., 2005

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Memetic Algorithm Based Path Planning for a Mobile Robot.

[BibT_eX]

Proceedings of the International Conference on Computational Intelligence, 2004

Instruction level test methodology for CPU core software-based self-testing.

[BibT_eX]

[DOI]

Saeed Shamshiri

Zainalabedin Navabi

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

[BibT_eX]

[DOI]

Saeed Shamshiri

Zainalabedin Navabi

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A novel improvement technique for high-level test synthesis.

[BibT_eX]

[DOI]

Saeed Safari

Amir-Hossein Jahangir

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Testability Improvement During High-Level Synthesis.

[BibT_eX]

[DOI]

Saeed Safari