Amirali Ghofrani

According to our database1, Amirali Ghofrani authored at least 19 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
Associative Memristive Memory for Approximate Computing in GPUs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A low-power hybrid reconfigurable architecture for resistive random-access memories.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory.
ACM J. Emerg. Technol. Comput. Syst., 2015

Architecting energy efficient crossbar-based memristive random-access memories.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A configurable CMOS memory platform for 3D-integrated memristors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Approximate associative memristive memory for energy-efficient GPUs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

HReRAM: a hybrid reconfigurable resistive random-access memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Toward large-scale access-transistor-free memristive crossbars.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Towards data reliable crossbar-based memristive memories.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
Comprehensive online defect diagnosis in on-chip networks.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
End-to-end error correction and online diagnosis for on-chip networks.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Assertion based verification in TLM.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

A TLM2.0 assertion library with centralized monitoring approach.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009


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