Sahand Salamat

Orcid: 0000-0002-3022-8212

According to our database1, Sahand Salamat authored at least 24 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD.
ACM Trans. Reconfigurable Technol. Syst., 2022

Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy.
ACM Trans. Embed. Comput. Syst., 2022

2021
Fast and Energy Efficient Big Data Processing on FPGAs
PhD thesis, 2021

Revisiting HyperDimensional Learning for FPGA and Low-Power Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

FPGA Acceleration of Protein Back-Translation and Alignment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

HyperRec: Efficient Recommender Systems with Hyperdimensional Computing.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
QuantHD: A Quantization Framework for Hyperdimensional Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Hyperdimensional Computing on FPGAs by Exploiting Computational Reuse.
IEEE Trans. Computers, 2020

SHEARer: Highly-Efficient Hyperdimensional Computing by Software-Hardware Enabled Multifold Approximation.
CoRR, 2020

FPGA Acceleration of Sequence Alignment: A Survey.
CoRR, 2020

SHEAR<i>er</i>: highly-efficient hyperdimensional computing by software-hardware enabled multifold approximation.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Revisiting FPGA Routing under Varying Operating Conditions.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

FPGA Energy Efficiency by Leveraging Thermal Margin.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms.
Proceedings of the International Conference on Computer-Aided Design, 2019

F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
RNSnet: In-Memory Neural Network Acceleration Using Residue Number System.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

2017
Systematic approximate logic optimization using don't care conditions.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017


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