Seonyong Cha
According to our database1,
Seonyong Cha
authored at least 12 papers
between 2022 and 2025.
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Bibliography
2025
30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays.
Proceedings of the IEEE International Memory Workshop, 2024
Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell.
Proceedings of the IEEE International Memory Workshop, 2024
Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform.
Proceedings of the IEEE International Memory Workshop, 2024
2023
QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Demonstration of crystalline IGZO transistor with high thermal stability for memory applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $\mathsf{i}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Recognition Accuracy Enhancement using Interface Control with Weight Variation-Lowering in Analog Computation-in-Memory.
Proceedings of the IEEE International Memory Workshop, 2022
Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges.
Proceedings of the IEEE International Memory Workshop, 2022