Brojo Gopal Sapui

Orcid: 0009-0003-2657-4205

According to our database1, Brojo Gopal Sapui authored at least 13 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
When Faults Don't Vanish: Persistent Fault Injection and Key Recovery on MRAM-Backed AES.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

HyFault: Targeted Fault Injection Attacks on Hyperdimensional Computing Accelerators.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Efficient Analog Error Correction for Printed Unary-Encoded Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

Collide & Conquer: Side-channel Attack on Hyper-dimensional Computing (HDC) Accelerators.
Proceedings of the IEEE International Test Conference in Asia, 2025

Leaks beyond Bits: Deep Learning-Assisted Side-Channel Attacks on Hyperdimensional Computing Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Invited Paper: Side Channel Vulnerability Analysis of Flexible Neuromorphic Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Side-channel Collision Attacks on Hyper-Dimensional Computing based on Emerging Resistive Memories.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Side-Channel Attack with Fault Analysis on Memristor-based Computation-in-Memory.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies.
Proceedings of the IEEE European Test Symposium, 2023

Highly-Bespoke Robust Printed Neuromorphic Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021
Introducing Recurrence in Strong PUFs for Enhanced Machine Learning Attack Resistance.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

2016
An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016


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