Mahta Mayahinia

Orcid: 0000-0002-6084-9810

According to our database1, Mahta Mayahinia authored at least 21 papers between 2020 and 2024.

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Bibliography

2024
Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture.
ACM J. Emerg. Technol. Comput. Syst., January, 2024

2023
Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration.
it Inf. Technol., May, 2023

A Low Overhead Checksum Technique for Error Correction in Memristive Crossbar for Deep Learning Applications.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies.
Proceedings of the IEEE European Test Symposium, 2023

On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI.
Proceedings of the IEEE European Test Symposium, 2023

Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.
Proceedings of the International Conference on Compilers, 2023

2022
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Voltage Tuning for Reliable Computation in Emerging Resistive Memories.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Analyzing the Electromigration Challenges of Computation in Resistive Memories.
Proceedings of the IEEE International Test Conference, 2022

An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.
Proceedings of the IEEE International Test Conference, 2022

A failure analysis framework of ReRAM In-Memory Logic operations.
Proceedings of the IEEE International Test Conference in Asia, 2022

Adaptive Block Error Correction for Memristive Crossbars.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Process and Runtime Variation Robustness for Spintronic-Based Neuromorphic Fabric.
Proceedings of the IEEE European Test Symposium, 2022

MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Data Leakage through Self-Terminated Write Schemes in Memristive Caches.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory.
Proceedings of the IEEE International Test Conference, 2021

2020
Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020


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