Shenggang Chen

According to our database1, Shenggang Chen authored at least 18 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication.
IEEE Trans. Parallel Distributed Syst., 2019

Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ANN Based Admission Control for On-Chip Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2016
Iteration Interleaving-Based SIMD Lane Partition.
ACM Trans. Archit. Code Optim., 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

2015
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
J. Softw., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng., 2015

Express Ring: a multi-layer and non-blocking NoC architecture.
IEICE Electron. Express, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2013
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Comput. Electr. Eng., 2013

2011
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

AIFSP: An Adaptive Instruction Flow Stream Processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era.
IEEE Trans. Circuits Syst. Video Technol., 2010

Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010

Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010


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