Siang-Yun Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions.

[BibT_eX]

[DOI]

Hanyu Wang

CoRR, 2023

2022

A Simulation-Guided Paradigm for Logic Synthesis and Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.

[BibT_eX]

[DOI]

Alessandro Tempia Calvino

CoRR, 2022

Majority-based Design Flow for AQFP Superconducting Family.

[BibT_eX]

[DOI]

Dewmini Sudara Marakkalage

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Beyond local optimality of buffer and splitter insertion for AQFP circuits.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.

[BibT_eX]

[DOI]

CoRR, 2021

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Simulation-Guided Boolean Resubstitution.

[BibT_eX]

[DOI]

CoRR, 2020

2019

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks.

[BibT_eX]

[DOI]

Nian-Ze Lee

Jie-Hong R. Jiang

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

Canonicalization of threshold logic representation and its applications.

[BibT_eX]

[DOI]