Heinz Riener

Akash Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

2022

A Simulation-Guided Paradigm for Logic Synthesis and Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.

[BibT_eX]

[DOI]

CoRR, 2022

Beyond local optimality of buffer and splitter insertion for AQFP circuits.

[BibT_eX]

[DOI]

Alessandro Tempia Calvino

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

A Versatile Mapping Approach for Technology Mapping and Graph Optimization.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Three-Input Gates for Logic Synthesis.

[BibT_eX]

[DOI]

Dewmini Sudara Marakkalage

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.

[BibT_eX]

[DOI]

Dewmini Sudara Marakkalage

CoRR, 2021

Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Safety Synthesis Sans Specification.

[BibT_eX]

[DOI]

CoRR, 2020

Simulation-Guided Boolean Resubstitution.

[BibT_eX]

[DOI]

CoRR, 2020

Automatic Uniform Quantum State Preparation Using Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Revisiting Explicit Enumeration for Exact Synthesis.

[BibT_eX]

[DOI]

Gianluca Martino

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Exact DAG-Aware Rewriting.

[BibT_eX]

[DOI]

Alan Mishchenko

Mathias Soeken

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle.

[BibT_eX]

[DOI]

Victor N. Kravets

Jie-Hong R. Jiang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Synthesizing adaptive test strategies from temporal logic specifications.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2019

Evaluating ESOP Optimization Methods in Quantum Compilation Flows.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 11th International Conference, 2019

Logic Optimization of Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Exact Synthesis of LTL Properties from Traces.

[BibT_eX]

[DOI]

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Exact Synthesis of ESOP Forms.

[BibT_eX]

[DOI]

CoRR, 2018

The EPFL Logic Synthesis Libraries.

[BibT_eX]

[DOI]

CoRR, 2018

Design Understanding: From Logic to Specification<sup>*</sup>.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Mining Latency Guarantees for RTL Designs.

[BibT_eX]

[DOI]

Jan Malburg

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017

Formal methods for automated debugging.

[BibT_eX]

[DOI]

PhD thesis, 2017

metaSMT: focus on your application and not on solver integration.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2017

Counterexample-Guided EF Synthesis of Boolean Functions.

[BibT_eX]

Rüdiger Ehlers

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification.

[BibT_eX]

[DOI]

Rüdiger Ehlers

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

WCET overapproximation for software in the context of a Cyber-Physical System.

[BibT_eX]

[DOI]

Niklas Krafczyk

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Counterexample-guided diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Exact diagnosis using boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Equivalence checking on ESL utilizing a priori knowledge.

[BibT_eX]

[DOI]

Niels Thole

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

SMT-Based CPS Parameter Synthesis.

[BibT_eX]

[DOI]

Proceedings of the ARCH@CPSWeek 2016, 2016

2015

Path-Based Program Repair.

[BibT_eX]

[DOI]

Rüdiger Ehlers

Proceedings of the Proceedings 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, 2015

Execution Tracing of C Code for Formal Analysis (Extended Abstract).

[BibT_eX]

Michael Kirkedal Thomsen

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Equivalence Checking on System Level Using a Priori Knowledge.

[BibT_eX]

[DOI]

Niels Thole

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

A Logic for Cardinality Constraints (Extended Abstract).

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

MetaSMT: a unified interface to SMT-LIB2.

[BibT_eX]

[DOI]

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013

Yet a Better Error Explanation Algorithm (Extended Abstract).

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Improving fault tolerance utilizing hardware-software-co-synthesis.

[BibT_eX]

[DOI]

Stefan Frehse

Proceedings of the Design, Automation and Test in Europe, 2013

2012

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.

[BibT_eX]

[DOI]

Proceedings of the Model Checking Software - 19th International Workshop, 2012

Model-based diagnosis versus error explanation.

[BibT_eX]

[DOI]

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

2011

Test Case Generation from Mutants Using Model Checking Techniques.

[BibT_eX]

[DOI]

Roderick Bloem