Jie-Hong Roland Jiang

Proceedings of the 2024 International Symposium on Physical Design, 2024

Unifying Decision and Function Queries in Stochastic Boolean Satisfiability.

[BibT_eX]

[DOI]

Yu-Wei Fan

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

Circuit Learning: From Decision Trees to Decision Graphs.

[BibT_eX]

[DOI]

Yu-Shan Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A Resolution Proof System for Dependency Stochastic Boolean Satisfiability.

[BibT_eX]

[DOI]

Yun-Rong Luo

Che Cheng

J. Autom. Reason., September, 2023

Quantized Neural Network Synthesis for Direct Logic Circuit Implementation.

[BibT_eX]

[DOI]

Yu-Shan Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion.

[BibT_eX]

[DOI]

Tian-Fu Chen

Chun-Yu Wei

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration.

[BibT_eX]

[DOI]

Chun-Yu Wei

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Second-Order Quantified Boolean Logic.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver.

[BibT_eX]

[DOI]

Yu-Wei Fan

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT.

[BibT_eX]

[DOI]

Che Cheng

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation.

[BibT_eX]

[DOI]

Chia-Chih Chi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Homing Sequence Derivation With Quantified Boolean Satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Design and Automation for Quantum Computation and Quantum Technologies.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Quantifier Elimination in Stochastic Boolean Satisfiability.

[BibT_eX]

[DOI]

Hao-Ren Wang

Kuan-Hua Tu

Proceedings of the 25th International Conference on Theory and Applications of Satisfiability Testing, 2022

Partial Equivalence Checking of Quantum Circuits.

[BibT_eX]

[DOI]

Tian-Fu Chen

Min-Hsiu Hsieh

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2022

Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability.

[BibT_eX]

[DOI]

Cheng-Han Hsieh

Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

Language Equation Solving via Boolean Automata Manipulation.

[BibT_eX]

[DOI]

Wan-Hsuan Lin

Chia-Hsuan Su

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification.

[BibT_eX]

[DOI]

Chang-Jun Wang

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021

SAT-Based On-Track Bus Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Constraint Solving for Synthesis and Verification of Threshold Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Circuit-Based SAT Solver for Logic Synthesis.

[BibT_eX]

[DOI]

He-Teng Zhang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Compatible Equivalence Checking of X-Valued Circuits.

[BibT_eX]

[DOI]

Chung-Yang (Ric) Huang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Deep Integration of Circuit Simulator and SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation.

[BibT_eX]

[DOI]

Yuan-Hung Tsai

Chiao-Shan Jhang

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving.

[BibT_eX]

[DOI]

Pei-Wei Chen

Yu-Ching Huang

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation to a New Level.

[BibT_eX]

[DOI]

Yuan-Hung Tsai

Chiao-Shan Jhang

CoRR, 2020

Symbolic Gas Vulnerability Detection and Attack Synthesis.

[BibT_eX]

[DOI]

Min Hao Peng

Fang Yu

Proceedings of the 24th Pacific Asia Conference on Information Systems, 2020

Symbolic Uniform Sampling with XOR Circuits.

[BibT_eX]

[DOI]

Yen-Ting Lin

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning.

[BibT_eX]

[DOI]

Yu-Chou Lin

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle.

[BibT_eX]

[DOI]

Heinz Riener

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Engineering Change Order for Combinational and Sequential Design Rectification.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies.

[BibT_eX]

[DOI]

He-Teng Zhang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Time Multiplexing via Circuit Folding.

[BibT_eX]

[DOI]

Po-Chun Chien

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Circuit Learning for Logic Regression on High Dimensional Boolean Space.

[BibT_eX]

[DOI]

Pei-Wei Chen

Yu-Ching Huang

Cheng-Lin Lee

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits.

[BibT_eX]

[DOI]

Zi-Jun Lin

Wei-Chih Huang

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks.

[BibT_eX]

[DOI]

Siang-Yun Lee

Proceedings of the International Conference on Computer-Aided Design, 2019

Time-Frame Folding: Back to the Sequentiality.

[BibT_eX]

[DOI]

Po-Chun Chien

Proceedings of the International Conference on Computer-Aided Design, 2019

Comprehensive Search for ECO Rectification Using Symbolic Sampling.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis.

[BibT_eX]

[DOI]

Hao Chen

Shao-Chun Hung

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Cube Distribution Approach to QBF Solving and Certificate Minimization.

[BibT_eX]

[DOI]

Li-Cheng Chen

Proceedings of the Principles and Practice of Constraint Programming, 2019

Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity.

[BibT_eX]

[DOI]

Wei-Chih Huang

Franck Molina

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.

[BibT_eX]

[DOI]

Yi-Fan Evan Chang

Ruei-Yang Huang

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

An approximation algorithm to the optimal switch control of reconfigurable battery packs.

[BibT_eX]

[DOI]

Shih-Yu Chen

Shou-Hung Welkin Ling

Shih-Hao Liang

Mao-Cheng Huang

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving.

[BibT_eX]

[DOI]

Ralf Wimmer

Aile Ge-Ernst

Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018

Towards Formal Evaluation and Verification of Probabilistic Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A symbolic model checking approach to the analysis of string and length constraints.

[BibT_eX]

[DOI]

Proceedings of the 33rd ACM/IEEE International Conference on Automated Software Engineering, 2018

Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection.

[BibT_eX]

[DOI]

Yen-Shi Wang

Proceedings of the Twenty-Seventh International Joint Conference on Artificial Intelligence, 2018

Static detection of API call vulnerabilities in iOS executables.

[BibT_eX]

[DOI]

Chun-Han Lin

Fang Yu

Tevfik Bultan

Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings, 2018

Canonicalization of threshold logic representation and its applications.

[BibT_eX]

[DOI]

Siang-Yun Lee

Proceedings of the International Conference on Computer-Aided Design, 2018

Cost-aware patch generation for multi-target function rectification of engineering change orders.

[BibT_eX]

[DOI]

He-Teng Zhang

Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient computation of ECO patch functions.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning.

[BibT_eX]

[DOI]

Hsiao-Lei Chien

Mei-Yen Chiu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Homing Sequence Derivation with Quantified Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Testing Software and Systems, 2017

Solving Stochastic Boolean Satisfiability under Random-Exist Quantification.

[BibT_eX]

[DOI]

Yen-Shi Wang

Proceedings of the Twenty-Sixth International Joint Conference on Artificial Intelligence, 2017

Sequential engineering change order under retiming and resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits.

[BibT_eX]

[DOI]

Cheng-Yu Shih

Chun-Hong Shih

Proceedings of the 54th Annual Design Automation Conference, 2017

Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation.

[BibT_eX]

[DOI]

Chun-Ning Lai

Proceedings of the 54th Annual Design Automation Conference, 2017

Recombinase-based genetic circuit optimization.

[BibT_eX]

[DOI]

Chun-Ning Lai

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines.

[BibT_eX]

[DOI]

Chun-Hong Shih

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016

Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.

[BibT_eX]

[DOI]

Chi-Chuan Chuang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification.

[BibT_eX]

[DOI]

Chi-Yuan Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Flexibility and Optimization of QBF Skolem-Herbrand Certificates.

[BibT_eX]

[DOI]

Shuo-Ren Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2QBF: Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Design partitioning for large-scale equivalence checking and functional correction.

[BibT_eX]

[DOI]

Grace Wu

Yi-Tin Sun

Proceedings of the 53rd Annual Design Automation Conference, 2016

String Analysis via Automata Manipulation with Logic Circuit Representation.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 28th International Conference, 2016

Clauses Versus Gates in CEGAR-Based 2QBF Solving.

[BibT_eX]

[DOI]

Proceedings of the Beyond NP, 2016

2015

Hybrid Simulations of Heterogeneous Biochemical Models in SBML.

[BibT_eX]

[DOI]

Sylvain Soliman

ACM Trans. Model. Comput. Simul., 2015

Deriving Compositionally Deadlock-Free Components over Synchronous Automata Compositions.

[BibT_eX]

[DOI]

Comput. J., 2015

QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving.

[BibT_eX]

[DOI]

Kuan-Hua Tu

Tzu-Chien Hsu

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis.

[BibT_eX]

[DOI]

Chun-Hong Shih

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines.

[BibT_eX]

[DOI]

Chi-Chuan Chuang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols.

[BibT_eX]

[DOI]

Bo-Yuan Huang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Property-Directed Synthesis of Reactive Systems from Safety Specifications.

[BibT_eX]

[DOI]

Ting-Wei Chiang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Reconfigurable neuromorphic computation in biochemical systems.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Scalable sequence-constrained retention register minimization in power gating design.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs.

[BibT_eX]

[DOI]

Mikolas Janota

Magdalena Widl

Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, 2015

2014

Henkin quantifiers and Boolean formulae: A certification perspective of DQBF.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2014

QBF Resolution Systems and Their Proof Complexities.

[BibT_eX]

[DOI]

Magdalena Widl

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2014, 2014

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification.

[BibT_eX]

[DOI]

Chi-Yuan Liu

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.

[BibT_eX]

[DOI]

Chi-Chuan Chuang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Building reconfigurable circuitry in a biochemical world.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Software Workarounds for Hardware Errors: Instruction Patch Synthesis.

[BibT_eX]

[DOI]

Tsung-Po Liu

Shuo-Ren Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Functional Timing Analysis Made Fast and General.

[BibT_eX]

[DOI]

Yi-Ting Chung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Encoding multi-valued functions for symmetry.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Automatic test pattern generation for delay defects using timed characteristic functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Synthesizing multiple boolean functions using interpolation on a single proof.

[BibT_eX]

[DOI]

Georg Hofferek

Ashutosh Gupta

Bettina Könighofer

Roderick Bloem

Proceedings of the Formal Methods in Computer-Aided Design, 2013

Synthesis of feedback decoders for initialized encoders.

[BibT_eX]

[DOI]

Kuan-Hua Tu

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models.

[BibT_eX]

[DOI]

Sylvain Soliman

Proceedings of the Computational Methods in Systems Biology, 2013

2012

Automatic Decoder Synthesis: Methods and Case Studies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders.

[BibT_eX]

[DOI]

Kuan-Hsien Ho

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Unified QBF certification and its applications.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2012

Henkin Quantifiers and Boolean Formulae.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Reducing test point overhead with don't-cares.

[BibT_eX]

[DOI]

Kai-Hui Chang

Chia-Wei Chang

Chien-Nan Jimmy Liu

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Improving design verifiability by early RTL coverability analysis.

[BibT_eX]

[DOI]

Kai-Hui Chang

Chia-Wei Chang

Chien-Nan Jimmy Liu

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Compiling program control flows into biochemical reactions.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way.

[BibT_eX]

[DOI]

Cheng-Shen Han

Proceedings of the Computer Aided Verification - 24th International Conference, 2012

Clock rescheduling for timing engineering change orders.

[BibT_eX]

[DOI]

Kuan-Hsien Ho

Xin-Wei Shih

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Scalable don't-care-based logic optimization and resynthesis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization.

[BibT_eX]

[DOI]

Chia-Wei Chang

Hong-Zu Chou

Kai-Hui Chang

Chien-Nan Jimmy Liu

Chiu-Han Hsiao

Sy-Yen Kuo

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Towards completely automatic decoder synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Resolution Proofs and Skolem Functions in QBF Evaluation and Applications.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2010

To SAT or Not to SAT: Scalable Exploration of Functional Dependency.

[BibT_eX]

[DOI]

Chih-Chun Lee

Chung-Yang Huang

IEEE Trans. Computers, 2010

A robust functional ECO engine by SAT proof minimization and interpolation techniques.

[BibT_eX]

[DOI]

Bo-Han Wu

Chun-Ju Yang

Chung-Yang Huang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Boolean matching of function vectors with strengthened learning.

[BibT_eX]

[DOI]

Chih-Fan Lai

Kuo-Hua Wang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

BooM: a decision procedure for boolean matching with abstraction and dynamic learning.

[BibT_eX]

[DOI]

Chih-Fan Lai

Kuo-Hua Wang

Proceedings of the 47th Design Automation Conference, 2010

Hardware Equivalence and Property Verification.

[BibT_eX]

[DOI]

Tiziano Villa

Yves Crama

Peter L. Hammer

Proceedings of the Boolean Models and Methods in Mathematics, 2010

2009

Interpolating functions from large Boolean relations.

[BibT_eX]

[DOI]

Hsuan-Po Lin

Wei-Lun Hung

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Quantifier Elimination via Functional Composition.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008

A dynamic accuracy-refinement approach to timing-driven technology mapping.

[BibT_eX]

[DOI]

Sz-Cheng Huang

Proceedings of the 26th International Conference on Computer Design, 2008

To SAT or not to SAT: Ashenhurst decomposition in a large scale.

[BibT_eX]

[DOI]

Hsuan-Po Lin

Ruei-Rung Lee

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Bi-decomposing large Boolean functions via interpolation and satisfiability solving.

[BibT_eX]

[DOI]

Ruei-Rung Lee

Wei-Lun Hung

Proceedings of the 45th Design Automation Conference, 2008

2007

Quantum Mechanical Search and Harmonic Perturbation.

[BibT_eX]

[DOI]

Dah-Wei Chiou

Cheng-En Wu

Quantum Inf. Process., 2007

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.

[BibT_eX]

[DOI]

Chin-Hsiung Hsu

Szu-Jui Chou

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Scalable exploration of functional dependency by interpolation and incremental SAT solving.

[BibT_eX]

[DOI]

Chih-Chun Lee

Chung-Yang Huang

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Inductive equivalence checking under retiming and resynthesis.

[BibT_eX]

[DOI]

Wei-Lun Hung

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Retiming and Resynthesis: A Complexity Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

On Some Transformation Invariants Under Retiming and Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

Efficient Solution of Language Equations Using Partitioned Representations.

[BibT_eX]

[DOI]

Tiziano Villa

Nina Yevtushenko

Proceedings of the 2005 Design, 2005

2004

On breakable cyclic definitions.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Functional Dependency for Verification Reduction.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

On the verification of sequential equivalence.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Reducing Multi-Valued Algebraic Operations to Binary.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Optimization of Multi-Valued Multi-Level Networks.

[BibT_eX]

[DOI]

M. Gao

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

Unified functional decomposition via encoding for FPGA technology mapping.

[BibT_eX]

[DOI]

Jing-Yang Jou

Juinn-Dar Huang

IEEE Trans. Very Large Scale Integr. Syst., 2001

1999

Optimum loading dispersion for high-speed tree-type decision circuitry.

[BibT_eX]

[DOI]

Iris Hui-Ru Jiang

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.

[BibT_eX]

[DOI]