Samah Mohamed Saeed

According to our database1, Samah Mohamed Saeed authored at least 29 papers between 2010 and 2020.

Collaborative distances:



In proceedings 
PhD thesis 




Analysis of Test Data Tampering Attack on Manufacturing Testing.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Reversible Circuits: IC/IP Piracy Attacks and Countermeasures.
IEEE Trans. Very Large Scale Integr. Syst., 2019

CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

Locking the Design of Building Blocks for Quantum Circuits.
ACM Trans. Embed. Comput. Syst., 2019

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2019

IC/IP piracy assessment of reversible logic.
Proceedings of the International Conference on Computer-Aided Design, 2018

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers.
IEEE Trans. Emerg. Top. Comput., 2017

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications.
IEEE Des. Test, 2017

Towards Reverse Engineering Reversible Logic.
CoRR, 2017

On the Difficulty of Inserting Trojans in Reversible Computing Architectures.
CoRR, 2017

Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Thwarting timing attacks on NEMS relay based designs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Activation of logic encrypted chips: Pre-test or post-test?
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Timing attack on NEMS relay based design of AES.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Test-mode-only scan attack and countermeasure for contemporary scan architectures.
Proceedings of the 2014 International Test Conference, 2014

DfST: Design for secure testability.
Proceedings of the 2014 International Test Conference, 2014

New scan attacks against state-of-the-art countermeasures and DFT.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Slack removal for enhanced reliability and trust.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Predictive Techniques for Projecting Test Data Volume Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Expedited-compact architecture for average scan power reduction.
IEEE Des. Test, 2013

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New scan-based attack using only the test mode.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Scan attack in presence of mode-reset countermeasure.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Multi-modal response compaction adaptive to x-density variation.
IET Comput. Digit. Tech., 2012

DfT support for launch and capture power reduction in launch-off-capture testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

Expedited response compaction for scan power reduction.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

XOR-Based Response Compactor Adaptive to X-Density Variation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010