Samah Mohamed Saeed

Orcid: 0000-0002-8107-3644

According to our database1, Samah Mohamed Saeed authored at least 41 papers between 2010 and 2023.

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Bibliography

2023
Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022
Test Points for Online Monitoring of Quantum Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2022

Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation.
CoRR, 2022

Towards Yield Improvement for AI Accelerators: Analysis and Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Machine Learning for Quantum Hardware Performance Assessment.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Graph Neural Networks for Idling Error Mitigation.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Automated Flag Qubit Insertion for Reliable Quantum Circuit Output.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Decomposition-Based Watermarking of Quantum Circuits.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
On the Difficulty of Inserting Trojans in Reversible Computing Architectures.
IEEE Trans. Emerg. Top. Comput., 2020

An Attack on Quantum Circuits Based on the Error Rates of NISQ Systems and a Countermeasure.
Proceedings of the Silicon Valley Cybersecurity Conference - First Conference, 2020

A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Analysis of Test Data Tampering Attack on Manufacturing Testing.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures.
IEEE Trans. Very Large Scale Integr. Syst., 2019

CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

Locking the Design of Building Blocks for Quantum Circuits.
ACM Trans. Embed. Comput. Syst., 2019

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2019

2018
IC/IP piracy assessment of reversible logic.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers.
IEEE Trans. Emerg. Top. Comput., 2017

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications.
IEEE Des. Test, 2017

Towards Reverse Engineering Reversible Logic.
CoRR, 2017

Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Thwarting timing attacks on NEMS relay based designs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Activation of logic encrypted chips: Pre-test or post-test?
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Timing attack on NEMS relay based design of AES.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

2014
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Test-mode-only scan attack and countermeasure for contemporary scan architectures.
Proceedings of the 2014 International Test Conference, 2014

DfST: Design for secure testability.
Proceedings of the 2014 International Test Conference, 2014

New scan attacks against state-of-the-art countermeasures and DFT.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Slack removal for enhanced reliability and trust.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013
Predictive Techniques for Projecting Test Data Volume Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Expedited-compact architecture for average scan power reduction.
IEEE Des. Test, 2013

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New scan-based attack using only the test mode.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Scan attack in presence of mode-reset countermeasure.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
Multi-modal response compaction adaptive to x-density variation.
IET Comput. Digit. Tech., 2012

DfT support for launch and capture power reduction in launch-off-capture testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Expedited response compaction for scan power reduction.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
XOR-Based Response Compactor Adaptive to X-Density Variation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010


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